Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1577090
date_generatedFri Jul 31 11:07:52 2020 os_platformWIN64
product_versionVivado v2016.2 (64-bit) project_id3d1a9dd28a6d47f28c6bb7613353c026
project_iteration8 random_id4d18922f3c615005bcc635548d08d296
registration_id4d18922f3c615005bcc635548d08d296 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-2
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-9400 CPU @ 2.90GHz cpu_speed2904 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
other_data
guimode=6
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=2 export_simulation_ies=2
export_simulation_modelsim=2 export_simulation_questa=2 export_simulation_riviera=2 export_simulation_vcs=2
export_simulation_xsim=2 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=9 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=5 carry4=22 fdce=7841 fdpe=231
fdre=340 gnd=18 ibuf=21 lut1=68
lut2=538 lut3=2007 lut4=1406 lut5=4603
lut6=4943 mmcme2_adv=1 muxf7=272 obuft=21
ramb36e1=7 srl16e=4 vcc=102
pre_unisim_transformation
bufg=5 carry4=22 fdce=7841 fdpe=231
fdre=340 gnd=18 ibuf=21 lut1=68
lut2=538 lut3=2007 lut4=1406 lut5=4603
lut6=4943 mmcme2_adv=1 muxf7=272 obuft=21
ramb36e1=7 srl16e=4 vcc=102

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=12 bram_ports_total=14 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=8410 srls_augmented=0
srls_newly_gated=0 srls_total=4

ip_statistics
blk_mem_gen_v7_3/1
c_addra_width=3 c_addrb_width=3 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=[user-defined]
c_enable_32bit_address=0 c_family=zynq c_has_axi_id=0 c_has_ena=0
c_has_enb=1 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=1 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=8 c_read_depth_b=8 c_read_width_a=72
c_read_width_b=72 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=8
c_write_depth_b=8 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=72
c_write_width_b=72 c_xdevicefamily=zynq core_container=NA iptotal=2
blk_mem_gen_v7_3/2
c_addra_width=6 c_addrb_width=6 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=[user-defined]
c_enable_32bit_address=0 c_family=zynq c_has_axi_id=0 c_has_ena=1
c_has_enb=0 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=0 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=64 c_read_depth_b=64 c_read_width_a=72
c_read_width_b=72 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=GENERATE_X_ONLY c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=64
c_write_depth_b=64 c_write_mode_a=READ_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=72
c_write_width_b=72 c_xdevicefamily=zynq core_container=NA iptotal=1
blk_mem_gen_v7_3/3
c_addra_width=7 c_addrb_width=7 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=[user-defined]
c_enable_32bit_address=0 c_family=zynq c_has_axi_id=0 c_has_ena=1
c_has_enb=1 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=1 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=128 c_read_depth_b=128 c_read_width_a=64
c_read_width_b=64 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=GENERATE_X_ONLY c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=128
c_write_depth_b=128 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=64
c_write_width_b=64 c_xdevicefamily=zynq core_container=NA iptotal=1
blk_mem_gen_v7_3/4
c_addra_width=6 c_addrb_width=6 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=[user-defined]
c_enable_32bit_address=0 c_family=zynq c_has_axi_id=0 c_has_ena=1
c_has_enb=1 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=1 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=64 c_read_depth_b=64 c_read_width_a=64
c_read_width_b=64 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=GENERATE_X_ONLY c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=64
c_write_depth_b=64 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=64
c_write_width_b=64 c_xdevicefamily=zynq core_container=NA iptotal=2
blk_mem_gen_v7_3/5
c_addra_width=6 c_addrb_width=6 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_default_data=0 c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=[user-defined]
c_enable_32bit_address=0 c_family=zynq c_has_axi_id=0 c_has_ena=1
c_has_enb=1 c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0
c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0
c_has_rsta=0 c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_init_file=BlankString c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0
c_interface_type=0 c_load_init_file=0 c_mem_type=1 c_mux_pipeline_stages=0
c_prim_type=1 c_read_depth_a=64 c_read_depth_b=64 c_read_width_a=72
c_read_width_b=72 c_rst_priority_a=CE c_rst_priority_b=CE c_rst_type=SYNC
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=GENERATE_X_ONLY c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_wea_width=1 c_web_width=1 c_write_depth_a=64
c_write_depth_b=64 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST c_write_width_a=72
c_write_width_b=72 c_xdevicefamily=zynq core_container=NA iptotal=1
clk_wiz_v5_3_1/1
clkin1_period=83.333 clkin2_period=10.0 clock_mgr_type=NA component_name=pll0
core_container=false enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=3 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified]
results
cfgbvs-7=1 pdcn-1569=21 plck-12=1 reqp-181=4
reqp-1839=322 rpbf-3=41

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.014053 clocks=0.028663
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=High confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.098877 die=xc7a100tcsg324-2 dsp_output_toggle=12.500000 dynamic=0.449412
effective_thetaja=4.6 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.166378 input_toggle=12.500000
junction_temp=27.5 (C) logic=0.043839 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.146631 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.548289 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=csg324 pct_clock_constrained=7.000000 pct_inputs_defined=9
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.049848
simulation_file=None speedgrade=-2 static_prob=False temp_grade=commercial
thetajb=5.7 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=4.6 user_junc_temp=27.5 (C) user_thetajb=5.7 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.087248 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.018244 vccaux_total_current=0.105491 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000473 vccbram_static_current=0.000444 vccbram_total_current=0.000916 vccbram_voltage=1.000000
vccint_dynamic_current=0.136556 vccint_static_current=0.016394 vccint_total_current=0.152950 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.047072 vcco33_static_current=0.004000 vcco33_total_current=0.051072 vcco33_voltage=3.300000
version=2016.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=5 bufgctrl_util_percentage=15.63
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=16.67
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=7 block_ram_tile_util_percentage=5.19
ramb18_available=270 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=7 ramb36_fifo_util_percentage=5.19
ramb36e1_only_used=7
primitives
bufg_functional_category=Clock bufg_used=5 carry4_functional_category=CarryLogic carry4_used=22
fdce_functional_category=Flop & Latch fdce_used=7843 fdpe_functional_category=Flop & Latch fdpe_used=231
fdre_functional_category=Flop & Latch fdre_used=340 ibuf_functional_category=IO ibuf_used=21
lut1_functional_category=LUT lut1_used=64 lut2_functional_category=LUT lut2_used=539
lut3_functional_category=LUT lut3_used=1991 lut4_functional_category=LUT lut4_used=1408
lut5_functional_category=LUT lut5_used=4603 lut6_functional_category=LUT lut6_used=4943
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=272
obuft_functional_category=IO obuft_used=21 ramb36e1_functional_category=Block Memory ramb36e1_used=7
srl16e_functional_category=Distributed Memory srl16e_used=4
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=272 f7_muxes_util_percentage=0.86
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=12709 lut_as_logic_util_percentage=20.05 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=4 lut_as_memory_util_percentage=0.02 lut_as_shift_register_fixed=0 lut_as_shift_register_used=4
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=8414 register_as_flip_flop_util_percentage=6.64
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=12713 slice_luts_util_percentage=20.05
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=8414 slice_registers_util_percentage=6.64
fully_used_lut_ff_pairs_fixed=6.64 fully_used_lut_ff_pairs_used=340 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_used=12709 lut_as_logic_util_percentage=20.05
lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_used=4 lut_as_memory_util_percentage=0.02
lut_as_shift_register_fixed=0 lut_as_shift_register_used=4 lut_ff_pairs_with_one_unused_flip_flop_fixed=4 lut_ff_pairs_with_one_unused_flip_flop_used=5333
lut_ff_pairs_with_one_unused_lut_fixed=5333 lut_ff_pairs_with_one_unused_lut_used=5392 lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=5791 lut_flip_flop_pairs_util_percentage=9.13 slice_available=15850 slice_fixed=0
slice_used=3952 slice_util_percentage=24.93 slicel_fixed=0 slicel_used=2702
slicem_fixed=0 slicem_used=1250 unique_control_sets_used=386 using_o5_and_o6_fixed=386
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=4 using_o6_output_only_fixed=4
using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=11982880 bogomips=0 bram18=0 bram36=7
bufg=0 bufr=0 congestion_level=0 ctrls=386
dsp=0 effort=2 estimated_expansions=15332232 ff=8414
global_clocks=5 high_fanout_nets=3 iob=42 lut=13154
movable_instances=22459 nets=23030 pins=124443 pll=0
router_runtime=58.654000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tcsg324-2
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=fpga_top
-verilog_define=default::[not_specified]
usage
elapsed=00:02:32s hls_ip=0 memory_gain=966.637MB memory_peak=1199.105MB