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Field NameBitAccessDescription
Mask bit31:16RWWrite valid bit for each LSB 16 bits
The 16 bits map to corresponding LSB 16bits. Write 1 to valid the corresponding bit writing

Reserved

15:910

RO

RESERVED

AXI GLOBAL CLKEN

89

RW

AXI GLOBAL Hardware IP Clock Enable
0: Disable
1: Enable (default)

ICM CLKEN

78

RW

ICM Hardware IP Clock Enable
0: Disable
1: Enable (default)

L2SW CLKEN

67

RW

L2SW Hardware IP Clock Enable
0: Disable
1: Enable (default)

FPGA CLKEN

56

RW

FPGA Hardware IP Clock Enable
0: Disable
1: Enable (default)

FIO CTL CLKEN

45

RW

FIO CTL Hardware IP Clock Enable
0: Disable
1: Enable (default)

DUMMY MASTER CLKEN

34

RW

DUMMY MASTER Hardware IP Clock Enable
0: Disable
1: Enable (default)

UADBG CLKEN

23

RW

UADBG Hardware IP Clock Enable
0: Disable
1: Enable (default)

DISP PWM CLKEN

12

RW

DISP PWM Hardware IP Clock Enable
0: Disable
1: Enable (default)

Reserved1RWRESERVED

OSD0 CLKEN

0

RW

OSD0 Hardware IP Clock Enable
0: Disable
1: Enable (default)

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