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...

Field Name

Bit

Access

Description

RSV

15:8

RO

Reserved

UD

7:0

RW

UART DATA

UART2 data transmit/receive FIFO port.Write to this register will store the written data to the output (TX) FIFO,
whereas read from this port will retrieve data from the input (RX) FIFO.If RXFIFO is empty, after reset operation,read data will be 0.

...

Field Name

Bit

Access

Description

RSV

15:8

RO

Reserved

TXE

6

RO

Transmit FIFO is Empty

0: Transmit FIFO is not empty.

1: Transmit-ended, transmit FIFO is empty.

BC

5

RO

Break Condition

0: No break condition.

1: A break condition occurs and associated byte is 00.

FE

4

RO

Frame Error

0: No frame error.

1: Frame error of current reading data.

OE

3

RO

Overrun Error

0: No overrun error since last read.

1: Overrun error occurs (clear upon read).

PE

2

RO

Parity Error

0: No Parity error.

1: Parity error occurs at current reading data.

RX

1

RO

Receive FIFO status

0: Receive FIFO is empty.

1: Receive FIFO not empty.

TX

0

RO

Transmit FIFO status

0: Transmit FIFO is full.

1: Transmit FIFO is not full (and available for more input).

...

Field Name

Bit

Access

Description

RSV

15:8

RO

Reserved

TE RI

7

RC

Trailing edge of Ring indicator

0: No Change.

1: Set when input RI B has changed from low to high state.

DT DCD

6

RC

Delta data carrie detect indicator

0: No Change.

1: Set when input DCD B has changed state.

DT CTS

5

RC

Delta clear to send indicator

0: No Change.

1: Set when input CTS B has changed state.

DT DSR

4

RC

Delta clear to send indicator

0: No Change.

1: Set when input DSR B has changed state.

RI

3

RO

RI indicator

Disable loop back mode, RI is the inverse of input port RI B. Enable loop back mode, RI is connected to bit 3 of MCR register.

DCD

2

RO

Data carrier detect

Disable loop back mode, DCD is the inverse of input port DCD B. Enable loop back mode, DCD is connected to bit 2 of MCR register.

CTS

1

RO

Clear to send

Disable loop back mode, CTS is the inverse of input port CTS B. Enable loop back mode, CTS is connected to RTS inter- nally.

DSR

0

RO

Data to ready

Disable loop back mode, DSR is the inverse of input port DSR B. Enable loop back mode, DSR is connected to DTR inter- nally.

...

Field Name

Bit

Access

Description

RSV

15:8

RO

Reserved

Vote

7:6

RW

Vote select (RXD noise rejection)

0x0: No major vote on uart2 RXD(default).

0x1: 3-sample vote.

0x2: 5-sample vote.

0x3: 7-sample vote.

BC

5

RW

Break condition select (START BIT)

0: No break condition(default).

1: Force serial output to spacing (low) state, break condi- tion.

RP

4

RW

Parity bit polarity select

0: Odd parity(default).

1: Even parity.

PE

3

RW

Parity bit enable

0: Disable parity bit(default).

1: Enable parity bit.

ST

2

RW

Number of stop bits

0: 1 stop bit(default).

1: For word length=5, 1.5 stop bits, for word length > 5, 2 stop bits.

WL

1:0

RW

Word length

0x0: 5bit.

0x1: 6bit.

0x2: 7bit.

0x3: 8bit(default).


16.4 UART2 Modem Control Register (uart2 mcr)

...

Field Name

Bit

Access

Description

RSV

15:8

RO

Reserved

AT

7

RW

AUTO CALIBRATE

0: No auto calibrate (or auto-calibration finished)(default).

1: Start baud-rate auto calibration. Calibration will stop after receive expected token (ASCII 'a' or 'A').

AC

6

RW

AUTO CTS mode

0: Disable CTS detection, TX FIFO sends out data al- ways(default).

1: Enable CTS detection, only send data when CTS B is active (low).

AR

5

RW

AUTO RTS mode

0: UART RTS B is controlled by RTS register(default).

1: UART RTS B is controlled by receive FIFO status.

LB

4

RW

MCR loop-back mode

0: Disable loop-back (normal function)(default).

1: Loop-back mode.
In loop-back mode:RXD, DSR, CTS = TXD, DTR, RTS.
RI, DCD = RI OUT, DCD OUT.
External output TXD = mark (high).External output DTR B,RTS B = inactive (high).

RI

3

RW

Ring-indicator register

0: UART RI inactive (output low)(default).

1: UART RI active (output high).

DCD

2

RW

Data carrier detect register

0: UART DCD B inactive (output high)(default).

1: UART DCD B active (output low).

RTS

1

RW

Request to send register (not used in AUTORTS mode)

0: UART RTS B inactive (output high)(default).

1: UART RTS B active (output low).

DTS

0

RW

Data terminal ready register

0: UART DTR B inactive (output high)(default).

1: UART DTR B active (output low).

...

Field Name

Bit

Access

Description

divisor ext[3:0]

15:12

RW

Extension of divisor[]

see divisor[7:0].

RSV

11:8

RO

Reserved

divisor[7:0]

7:0

RW

System clock divisor LSB
These 8 bits combined with System clock divisor MSB are used to generate the UART reference 16x over- sampling clock. baud rate = SYSCLK/ (16*(divisor[15:0]+1) + divisor ext[3:0]).

...

Field Name

Bit

Access

Description

RSV

15:8

RO

Reserved

MSM

7

RW

Modem Status interrupt Mask

0: INT disable(default).

1: INT enable.

LSM

6

RW

Line Status interrupt Mask

0: INT disable(default).

1: INT enable.

RXM

5

RW

RX interrupt Mask

0: INT disable(default).

1: INT enable.

TXM

4

RW

TX interrupt Mask

0: INT disable(default).

1: INT enable.

MS

3

RU

Modem status interrupt flag

This bit is set when any of DT DSR, DT CTS, DT DCD, or TE RI is one and MSR interrupt is enabled.

0: No modem status interrupt issued(default).

1: Modem status interrupt issued.

LS

2

RU

Line status interrupt flag

This bit is asserted when and of PE, FE, BC, OE condition occurred and LS interrupt is enable.

0: No line status interrupt issued(default).

1: Line status interrupt issued.

RX INT

1

RU

RX FIFO NOT EMPTY interrupt flag.

This bit is asserted when RX FIFO is not empty and RX interrupt enable.

0: No RX interrupt issued(default).

1: RX interrupt issued.

TX INT

0

RU

TX FIFO EMPTY interrupt flag.
This bit is asserted when TX FIFO is empty and TX interrupt is enable.
0: No TX interrupt issued(default).
1: TX interrupt issued.

...

Field Name

Bit

Access

Description

RSV

15:7

RO

Reserved

tx residue

6:0

RO

tx residue, TX FIFO flush

Read to get the remainder characters in the TX FIFO.
Write zero to flush TX FIFO, and write other values has no effect.

...

Field Name

Bit

Access

Description

RSV

15:7

RO

Reserved

rx residue

6:0

RO

rx residue, RX FIFO flush

Read to get the remainder characters in the RX FIFO.
Write zero to flush RX FIFO, and write other values has no effect.

...

Field Name

Bit

Access

Description

RSV

15:12

RO

Reserved

RXFIFO THRESHOLD

11:4

RW

RXFIFO Threshold Value

Set the remainder space in the RXFIFO.If the remaining space is less than RXFIFO THRESHOLD, it would assert interrupt when RXFIFO Threshold is enabled. unit : byte.

RSV

3:1

RO

Reserved

RXFIFO THR ENABLE

0

RW

RXFIFO Threshold Enable

0 : disable threshold control for RXFIFO(default).

1 : enable threshold control for RXFIFO.

...

Field Name

Bit

Access

Description

RSV

15:1

RO

Reserved

CLK BAUD

0

RW

UART CLK BAUD RATE SEL

0 : select to SYSCLK.

1 : 27MHz (default).


RGST Table Group 17 UART3 (Base Address: 0x9C000880, Please refer to UART2 register offset and description for more detail)
RGST Table Group 18 UART0 (Base Address: 0x9C000900, Please refer to UART2 register offset and description for more detail)
RGST Table Group 19 UART1 (Base Address: 0x9C000980, Please refer to UART2 register offset and description for more detail)
RGST Table Group 271 UART4  (Base Address: 0x9C008780, Please refer to UART2 register offset and description for more detail)



RGST Table Group 273 GDMA: General DMA (HWUA_GDMA0)

...

Field Name

Bit

Access

Description

DMA HW VER

31:0

RO

Hardware Version

A constant, usually stands for hw delivery date, such as 32'h01791000.

...

Field Name

Bit

Access

Description

Reserved

31:9

RO

Reserved

DMA GO

8

RUW

DMA GO Signal

Write 1 to trigger DMA hardware, self clear to zero when current operation has been finished.

Reserved

7:3

RO

Reserved

NON BUF MODE

2

RW

GDMA write command bufferable
0x0: all write command is bufferable
0x1: all write command is non-buffer(default)
Valid when DMA_GO been set to1, and can not be changed when DMA_GO assert.

SAME SLAVE

1

RW

GDMA access same slave
0x0: access different slave in SG mode (like CBDMA&DRAM at the same time)(default)
0x1: access same slave in SG mode
Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.

DMA MODE

0

RW

Set DMA Mode
0x0: DMA_READ(read data from main memory to internal SRAM)(default)
0x1: DMA_WRITE(write data from internal SRAM to main memory)
Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.

...

Field Name

Bit

Access

Description

Reserved

31:25

RO

Reserved

DMA LENGTH

24:0

RW

Set DMA Length

DMA read and write function support length.
Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.

...

Field Name

Bit

Access

Description

Reserved

31:7

RO

Reserved

LENGTH0 REG

6

W1C

Length is zero flag
In SG Mode: If RUN_LLI_INDEX length is zero, the LENGTH0_REG will 1.
In Normal Mode: If length is zero, the LENGTH0_REG will be 1.

THRESHOLD REG

5

W1C

Threshold flag
In SG Mode: When RUN_LLI_INDEX=THRESHOLD_LLI_INDEX and NUM=THRESHOLD_NUM, the interrupt will occurs.
In Normal Mode: When NUM=THRESHOLD_NUM, the interrupt will occurs.

IP TIMEOUT REG

4

W1C

Peripheral IP Timeout

When GDMA wait Peripheral IP too long will set HIGH, depend on IP_TIMEOUT_DEF_WRITE and IP_TIMEOUT_DEF_READ.

GDMA TIMEOUT REG

3

W1C

GDMA Timeout

When Peripheral IP wait GDMA too long will set HIGH, depend on GDMA_TIMEOUT_DEF_WRITE and GDMA_TIMEOUT_DEF_READ.

WRITE BYTE ENABLE ERROR REG

2

W1C

Peripheral IP WRITE_BYTE_EN error flag

WRITE_BYTE_EN not meet the protocol.

WRITE CNT

1

W1C

Peripheral IP DATA CNT error flag

Data Count error.

DMA DONE FLAG

0

W1C

DMA DONE

If DMA done, this bit will be assert. Write 1 to clear.

...

Field Name

Bit

Access

Description

D0INT

31

RU

DMA0 INT

0: Clear by DMA INT CLR(default).

1: Clear INT State,DMA STATE wait for DMA GO.

RSV

30:21

RO

Reserved

D0OFC

20

RW

DMA0 OVER FLOW CONFIG

judge the fifo threshold, stop the dma access or not when interrupt is occur.

RSV

19

RO

Reserved

D0MI

18:12

RW

DMA0 MSI ID

DMA0 setting MSI ID.

RSV

11

RO

Reserved

D0SU

10:8

RW

DMA0 SELECT UART

DMA0 select UA# RN, # is from 0 to 5.

D0SRB

7

RW

DMA0 SOFT RESET.

0: active reset and back to initial-DMA.

  • DMA WR ADDR[31:0] = DMA START ADDR[31:0]. DMA DATABYTES[15:0] = 0.
  • DMA SW RST B usage steps: a. UADMA AUTO ENABLE == 0. b. When DMA DEBUG INFO == c dma stage[3:0] is 0. c. Set DMA SW RSTB == 0 - 1. d. initial UADMA state.

1: normal work(default).

D0INIT

6

RW

DMA0 INITIAL

BEFORE DMA FIRST GO, It NEED SETTING INITIAL SETTING.

0: DMA not initial(default).

1: DMA INIT, write 1 to initialize DMA and followed by writing 0 to finish initialization.

After initializedDMA WR ADDR[31:0]==DMA START ADDR[31:0]
DMA RD ADDR[31:0]==DMA START ADDR[31:0]

D0GO

5

RU

DMA0 GO

0: it will return to 0 automatically after triggered to 1(default).

1: DMA continue/start

D0AE

4

RW

DMA0 AUTO ENABLE

0: Disable DMA0 Engine(default).

1: Enable DMA0 Engine.

D0TIE

3

RW

DMA0 TIMEOUT INT EN

0: time out no issue interrupt(default).

1: time out issue interrupt.

D0PSD

2

RW

DMA0 P SAFE DISABLE

0: when every pbus traffic issue write flush and msi command, it's say that the data write into DRAM will be send MSI cmd(default).

1: when data bytes reach to thread x 2, issue write flush and msi command.

D0PS

1

W

DMA0 PBUS DATA SWAP

0:PBUS DATA[15:0] == "Byte0 , Byte1"(default).

1:PBUS DATA[15:0] == "Byte1 , Byte0".

D0EN

0

RW

DMA0 ENABLE

0: Disable UA# Data to DMA0(default).

1: Enable UA# Data to DMA0.

...

Field Name

Bit

Access

Description

D0RA

31:0

RW

DMA0 Read Address

DMA(CPU) read out address. <It had read>.

...

Field Name

Bit

Access

Description

D0DB

15:0

RO

DMA0 DATABYTES

Data Bytes in DMA0 SPACE


275.9 RESERVED  (reserved)
Address: 0x9C0089A4 
Reset: 0x0

...

Field Name

Bit

Access

Description

D1INT

31

RU

DMA1 INT

0: Clear by DMA INT CLR(default).

1: Clear INT State,DMA STATE wait for DMA GO.

RSV

30:21

RO

Reserved

D1OFC

20

RW

DMA1 OVER FLOW CONFIG

judge the fifo threshold, stop the dma access or not when interrupr is occur.

RSV

19

RO

Reserved

D1MI

18:12

RW

DMA1 MSI ID

Set MSI ID for DMA1. 

RSV

11

RO

Reserved

D1SU

10:8

RW

DMA1 SELECT UART

DMA1 select UA# RN, # is from 0 to 5.

D1SRB

7

RW

DMA1 SOFT RESET.

0: active reset and back to initial-DMA.

  • DMA WR ADDR[31:0] = DMA START ADDR[31:0]. DMA DATABYTES[15:0] = 0.
  • DMA SW RST B usage steps: a. UADMA AUTO ENABLE == 0. b. When DMA DEBUG INFO == c dma stage[3:0] is 0. c. Set DMA SW RSTB == 0 - 1. d. initial UADMA state.

1: normal work(default).

D1INIT

6

RW

DMA1 INITIAL

Before DMA first GO, It need set initial at first.

0: DMA not initial(default).

1: DMA INIT
Write 1 for DMA initial, than write 0 to finish initial. (DMA WR ADDR[31:0]==DMA START ADDR[31:0]) (DMA RD ADDR[31:0]==DMA START ADDR[31:0]).

D1GO

5

RU

DMA1 GO

0: it will return to 0 automatically after triggered to 1(default).

1: DMA continue/start , gen trigger pulse for toggle dma running.

D1AE

4

RW

DMA1 AUTO ENABLE

0: Disable DMA1 Engine(default).

1: Enable DMA1 Engine.

D1TIE

3

RW

DMA1 TIMEOUT INT EN

0: time out no issue interrupt(default).

1: time out issue interrupt.

D1PSD

2

RW

DMA1 PBUS SAFE DISABLE

0: when every pbus traffic, issue write flush and msi command(default).

1: when data bytes reach to thread x 2, issue write flush and msi command. 
PS. Threshold =threadx2, the threshold can be set at G275.22 (rf dma1 length thr) bit 15~0.

D1PDS

1

RW

DMA1 PBUS DATA SWAP

0:PBUS DATA[15:0] == "Byte0 , Byte1"(default).

1:PBUS DATA[15:0] == "Byte1 , Byte0".

D1EN

0

RW

DMA1 ENABLE

0: Disable UA# Data to DMA1(default).

1: Enable UA# Data to DMA1.

...

Field Name

Bit

Access

Description

D1RA

31:0

RW

DMA1 RD ADDR

DMA(CPU) read out address. <It had read>.

...

Field Name

Bit

Access

Description

RCGDMA0EN

31

RC

REDO ENABLE

After the error interrupt that HW_BUF_UA need to redo by CPU at DEBUG mode.

RSV

30:3

RO

Reserved

GDMA0RDEN

2

RW

GDMA0 READ ENABLE

Determine the GDMA0 read access when read enable is assert.

GDMA0WREN

1

RW

GDMA0 WRITE ENABLE

Determine the GDMA0 write access when write enable is assert.

GDMA0DEN

0

RW

GDMA0 DEBUG ENABLE

Determine the HW_BUF_UA access in debug mode when enable is assert.

...

Field Name

Bit

Access

Description

RSV

31:19

RO

Reserved

GDMA0SELUAWR

18:16

RW

GDMA0 SEL UARTX WR

If want access UA0, should setting the select[18:16] be 3'h0.
0x0:UART0
0x1:UART1
0x2:UART2
0x3:UART3
0x4:UART4

RSV

15:3

RO

Reserved

GDMA0SELUARD

2:0

RW

GDMA0 SEL UARTX RD

If want access UA0, should setting the select[2:0] be 3'h0.
0x0:UART0
0x1:UART1
0x2:UART2
0x3:UART3
0x4:UART4

...

Field Name

Bit

Access

Description

GDMA0SADR

31:0

RW

GDMA0 START ADDR

The ring buffer start addr that mapping to DRAM.

...

Field Name

Bit

Access

Description

GDMA0EADR

31:0

RW

GDMA0 END ADDR

The ring buffer end addr that mapping to DRAM.

...

Field Name

Bit

Access

Description

GDMA0WADR

31:0

RW

GDMA0 WRITE ADDR

The write address means that CPU write data address.

...

Field Name

Bit

Access

Description

GDMA0RADR

31:0

RW

GDMA0 READ ADDR

The read address means that CPU read data address.

...

Field Name

Bit

Access

Description

RSV

31:2

RO

Reserved

GDMA0EMP

1

RU

BUFFER EMPTY

Buffer on DRAM status is empty

GDMA0FUL

0

RU

BUFFER FULL

Buffer on DRAM status is full

...

Field Name

Bit

Access

Description

GDMA0TU

31:0

RW

GDMA0 TIMER UNIT

In HW_BUF_UA, the TIMER_UNIT has default value that is 1ms on 27MHz.

...

Field Name

Bit

Access

Description

GDMA0TC

31:0

RW

GDMA0 TIMER COUNT

The TIMER_COUNT is count by TIMER count to TIMER_UNIT

...

Field Name

Bit

Access

Description

RSV

31:1

RO

Reserved

GDMA0SRD

0

RO

GDMA0 SW RESET DONE

When occur error interrupt, CPU need to set SW_RESET that check the transaction is done or not between GDMA and bus termination.

...

Field Name

Bit

Access

Description

RCGDMA1EN

31

RC

REDO ENABLE

After the error interrupt that HW_BUF_UA need to redo by CPU at DEBUG mode.

RSV

30:3

RO

Reserved

GDMA1RDEN

2

RW

GDMA1 READ ENABLE

Determine the GDMA1 read access when read enable is assert.

GDMA1WREN

1

RW

GDMA1 WRITE ENABLE

Determine the GDMA1 write access when write enable is assert.

GDMA1DEN

0

RW

GDMA1 DEBUG ENABLE

Determine the HW_BUF_UA access in debug mode when enable is assert.

...

Field Name

Bit

Access

Description

RSV

31:19

RO

Reserved

GDMA1SELUAWR

18:16

RW

GDMA1 SEL UARTX WR

If want access UA0, should setting the select[18:16] be 3'h0.
0x0:UART0
0x1:UART1
0x2:UART2
0x3:UART3
0x4:UART4

RSV

15:3

RO

Reserved

GDMA1SELUARD

2:0

RW

GDMA1 SEL UARTX RD

If want access UA0, should setting the select[2:0] be 3'h0.
0x0:UART0
0x1:UART1
0x2:UART2
0x3:UART3
0x4:UART4

...

Field Name

Bit

Access

Description

GDMA1SADR

31:0

RW

GDMA1 START ADDR

The ring buffer start addr that mapping to DRAM.

...

Field Name

Bit

Access

Description

GDMA1EADR

31:0

RW

GDMA1 END ADDR

The ring buffer end addr that mapping to DRAM.

...

Field Name

Bit

Access

Description

GDMA1WADR

31:0

RW

GDMA1 WRITE ADDR

The write address means that CPU write data address.

...

Field Name

Bit

Access

Description

GDMA1RADR

31:0

RW

GDMA1 READ ADDR

The read address means that CPU read data address.

...

Field Name

Bit

Access

Description

RSV

31:2

RO

Reserved

GDMA1EMP

1

RU

BUFFER EMPTY

Buffer on DRAM status is empty

GDMA1FUL

0

RU

BUFFER FULL

Buffer on DRAM status is full

...

Field Name

Bit

Access

Description

GDMA1TU

31:0

RW

GDMA1 TIMER UNIT

In HW_BUF_UA, the TIMER_UNIT has default value that is 1ms on 27MHz.

...

Field Name

Bit

Access

Description

GDMA1TC

31:0

RW

GDMA1 TIMER COUNT

The TIMER_COUNT is count by TIMER count to TIMER_UNIT

...

Field Name

Bit

Access

Description

RSV

31:1

RO

Reserved

GDMA1SRD

0

RO

GDMA1 SW RESET DONE

When occur error interrupt, CPU need to set SW_RESET that check the transaction is done or not between GDMA and bus termination.

...