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Field Name	Bit	Access	Description
Reserved	31:7	RO	Reserved
LENGTH0 REG	6	W1C	Length is zero flag In SG Mode: If RUN_LLI_INDEX length is zero, the LENGTH0_REG will 1. In Normal Mode: If length is zero, the LENGTH0_REG will be 1.
THRESHOLD REG	5	W1C	Threshold flag In SG Mode: When RUN_LLI_INDEX=THRESHOLD_LLI_INDEX and NUM=THRESHOLD_NUM, the interrupt will occurs. In Normal Mode: When NUM=THRESHOLD_NUM, the interrupt will occurs.
IP TIMEOUT REG	4	W1C	Peripheral IP Timeout When GDMA wait Peripheral IP too long, this bit will be set to HIGH, depend . Depend on IP_TIMEOUT_DEF_WRITE and IP_TIMEOUT_DEF_READ.
GDMA TIMEOUT REG	3	W1C	GDMA Timeout When Peripheral IP wait GDMA too long will set HIGH, depend on GDMA_TIMEOUT_DEF_WRITE and GDMA_TIMEOUT_DEF_READ.
WRITE BYTE ENABLE ERROR REG	2	W1C	Peripheral IP WRITE_BYTE_EN error flag WRITE_BYTE_EN not meet the protocol.
WRITE CNT	1	W1C	Peripheral IP DATA CNT error flag Data Count error.
DMA DONE FLAG	0	W1C	DMA DONE If DMA done, this bit will be assert. Write 1 to clear.

273.5 6 DMA INT FLAGEN (dma int flagen)
Address: 0x9C0088940x9C008898

Reset: 0x0000 00000041

Field Name	Bit	Access	Description
Reserved	31:7	RO	Reserved
LENGTH0 REGEN	6	W1C	Length is zero flag In SG Mode: If RUN_LLI_INDEX length is zero, the LENGTH0_REG will 1. In Normal Mode: If length is zero, the LENGTH0_REG will be 1.RW	LENGTH0 Interrupt Enable Write 1 to enable LENGTH0 interrupt function.
THRESHOLD EN	5	RW	THRESHOLD Interrupt Enable Write 1 to enable THRESHOLD interrupt function.
IP TIMEOUT EN	4	RW	IP TIMEOUT Interrupt Enable Write 1 to enable IP_TIMEOUT interrupt function.
GDMA TIMEOUT EN	3	RW	GDMA TIMEOUT Interrupt Enable Write 1 to enable GDMA_TIMEOUT interrupt function.
WRITE BYTE ENABLE ERROR EN	2	RW	Write Byte ERROR Interrupt Enable Write 1 to enable WRITE_BYTE_ENABLE_ERROR interrupt function.
WRITE CNT ERROR EN	1	RW	Write CNT ERROR Interrupt Enable Write 1 to enable WRITE_CNT_ERROR interrupt function.
DMA DONE EN	0	RW	DMA DONE Interrupt Enable Write 1 to enable DMA_DONE interrupt function.

273.7 SW_RESET_STATE (software reset state)
Address: 0x9C00889C

Reset: 0x0000 0001

Field Name

Bit

Access

Description

Reserved

31:1

RO

Reserved

SW RESET DONE

0

RO

Identify SW_RESET state
0x0: resetting, need wait SW_RESET_DONE to be HIGH.

0x1: reset done, ready for SW_RESET.

273.8 Reserved (reserved)
Address: 0x9C0088A0

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:0	RO	Reserved

273.9 Reserved (reserved)
Address: 0x9C0088A4

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:0	RO	Reserved

273.10 SG_DMA_INDEX (sg_dma_index)
Address: 0x9C0088A8

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:13	RO	Reserved
SG LLI RUN INDEX	12:8	RW	The stare LLI index in a task If the task stop cause error occur, SG_LLI_RUN_INDEX will indicate which LLI fail.
Reserved	7:5	RO	Reserved
SG LLI ACCESS INDEX	4:0	RW	Index for LLI access Determine which LLI mapping to REG 0x0B 0x0F.

273.11 SG_DMA_CONFIG (sg_dma_config)
Address: 0x9C0088AC

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:3	RO	Reserved
SG LAST LLI IN TASK	2	RW	Last LLI in a task flag for LLI 0: When this LLI finish, execute next LLI.(default) 1: When this LLI finish, SGDMA stop.
Reserved	1	RO	Reserved
DMA MODE	0	RW	Set DMA Mode for LLI 0: DMA_WRITE (write data from Peripheral IP to main memory) 1: DMA_READ (read data from main memory to Peripheral IP)

273.12 SG_DMA_LENGTH (sg_dma_length)
Address: 0x9C0088B0

Reset: 0x0000 0000

Field Name

Bit

Access

Description

Reserved

31:25

RO

Reserved

SG DMA LENGTH

24:0

RW

Set DMA Length for LLI

DMA read and write function support length from 1bytes to 64Kbytes. Valid when DMA_GO is set to 1 and can't be changed when DMA_GO assert.

273.13 SG_DMA_ADR (sg_dma_adr)
Address: 0x9C0088B4

Reset: 0x0000 0000

Field Name	Bit	Access	Description
SG DMA ADR	31:0	RW	DMA address for LLI Valid when DMA_GO is set to 1 and can't be changed when DMA_GO assert.

273.14 Reserved (reserved)
Address: 0x9C0088B8

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:0	RO	Reserved

273.15 SG_SETTING (sg_setting)
Address: 0x9C0088BC

Reset: 0x0000 0000

Field Name	Bit	Access	Description
SG DMA ENABLE	31	RW	SG DMA ENABLE Set SG_DMA enable for LLI.
Reserved	30:1	RO	Reserved
SG DMA GO	0	RW	SG DMA GO Set SG_DMA_GO enable for LLI.

273.16 THRESHOLD (threshold_parameter)
Address: 0x9C0088C0

Reset: 0x0000 0000

Field Name	Bit	Access	Description
THRESHOLD LLI INDEX	31:27	RW	THRESHOLD LLI INDEX Determine the LLI index to trigger THRESHOLD INTERRUPT.
Reserved	26:25	RO	Reserved
THRESHOLD LEN	24:0	RW	THRESHOLD LENGTH Determine the length to trigger THRESHOLD INTERRUPT.

273.17 Reserved (reserved)
Address: 0x9C0088C4

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:0	RO	Reserved

273.18 GDMA_READ_TIMEOUT (gdma_read_timeout setting)
Address: 0x9C0088C8

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA READ TIMEOUT	31:0	RW	GDMA READ TIMEOUT DEFINE Define GDMA READ TIMEOUT counter, can't set 0, only can set when DMA_GO_IP=0.

273.19 GDMA_WRITE_TIMEOUT (gdma_write_timeout setting)
Address: 0x9C0088CC

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA WRITE TIMEOUT	31:0	RW	GDMA WRITE TIMEOUT DEFINE Define GDMA WRITE TIMEOUT counter, can't set 0, only can set when DMA_GO_IP=0.

273.20 IP_READ_TIMEOUT (ip_read_timeout setting)
Address: 0x9C0088D0

Reset: 0x0000 0000

Field Name	Bit	Access	Description
IP READ TIMEOUT	31:0	RW	IP READ TIMEOUT DEFINE Define IP READ TIMEOUT counter, can't set 0, only can set when DMA_GO_IP=0.

273.21 IP_WRITE_TIMEOUT (ip_write_timeout setting)
Address: 0x9C0088D4

Reset: 0x0000 0000

Field Name	Bit	Access	Description
IP WRITE TIMEOUT	31:0	RW	IPWRITE TIMEOUT DEFINE Define IP WRITE TIMEOUT counter, can't set 0, only can set when DMA_GO_IP=0.

273.22 WRITE_CNT_DEBUG information (write_cnt_debug)
Address: 0x9C0088D8

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserverd	31	RO	Reserved
WRITE CNT DEBUG	30:0	RO	WRITE_CNT_DEBUG When WRITE_CNT_ERROR happened, the write counter for debug.

273.23 WRITE_BYTE_ENABLE_DEBUG information (write_byte_enable_debug)
Address: 0x9C0088DC

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserverd	31:1	RO	Reserved
W_BYTE_EN_DEBUG	0	RO	WRITE_BYTE_ENABLE_DEBUG When WRITE_BYTE_ENABLE_ERROR happened, the write byte enable for debug.

273.24 SW_RESET_WRITE_CNT_DEBUG information (sw_reset_write_cnt_debug)
Address: 0x9C0088E0

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserverd	31:30	RO	Reserved
SW_RESET_WRITE_CNT_DEBUG	29:0	RO	SW _RESET WRITE CNT DEBUG When the SW_RESET error, the write counter for debug. GDMA send valid data to AXI slave.

RGST Table Group 274 GDMA: General DMA (HWUA_GDMA1) (Base Address: 0x9C008900, Please refer to HWUA_GDMA0 register offset and description for more detail)

RGST Table Group 275 UADMA

275.0 RF DMA0 ENABLE SEL (rf dma0 enable sel)
Address: 0x9C008980

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Old Version 13

New Version 14

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