Preface
This manual describes how to use the C3V-W Evaluation Board (EVB). This evaluation board is used for IP verification and software functions testing of the C3V-W chip. IP verification includes all IP tests in the chip, chip boot modes test, all GPIO, DVIO pins (UART, I2C, SPI, …) testing and multiplexed functional pins test, USB2.0, USB3.0, CPIO, MIPI/CSI-RX2, MIPI/CSI-RX3, MIPI/CSI-RX4, MIPI/CSI-RX5, MIPI/DSI-TX, and MIPI/CSI-TX and other interface tests. Software functions include i-boot, x-boot, U-Boot, TF-A, OP-TEE, FreeRTOS, Linux, Ubuntu server with MATE desktop and other related application tests.
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Items | Explanations |
1 | 12V DC power input. The diameter of the DC Jack plug is 5.5mm. The power supply current of the adapter must be greater than 1A. |
2 | Main-power switch. Turn left to ON, and turn right to OFF. Note that you still need to press Wake-up key (for 1 second) to wake up the system after turning on main-power switch. |
3 | Wake-up key. The functions are as follows:
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4 | Socket (DIP-8) of SPI-NOR flash chip. Before inserting the SPI-NOR flash chip, be sure to confirm the chip notch direction (or pin 1 position) and the chip power supply voltage (1.8V or 3.3V). There is a SOIC-8 soldering pad under the DIP-8 socket. The DIP-8 socket can be removed and used a SOIC-8 SPI-NOR chip instead Note that to test frequencies of SPI-NOR flash above 60MHz, please use SOIC-8 packaged chips. |
5 | Socket of micro SD card. |
6 | RJ-45 socket of Ethernet. It supports 10M/100M/1000M speeds. |
7 | Giga PHY chip of Ethernet (Realtek RTL8211FD). |
8 | Pin-header (3-pin, 100-mil, 3.3V) of UADBG/UA2AXI (serial port). The pin definitions from left to right are TX, RX, and GND. It can be used as general UART (UADBG) or UART-to-AXI bridge UART (UA2AXI). The default baud rate is 115,200. No parity and 1 stop-bit. Software uses it as an OP-TEE serial port interface for debugging client applications of OP-TEE. Please note that EVB does not use the UADBG/UA2AXI serial port by default. To use the UADBG/UA2AXI serial port, please solder 0Ω resistors at the R411 and R412 positions, and remove the 0Ω resistors at the R348 and R349 positions. In addition, be care of pin-mux settings in software, UADBG/UA2AXI cannot be used with the CA55 JTAG or GMAC interface at the same time. Make sure both CA55 JTAG and GMAC interfaces are off. |
9 | Socket (DIP-24, 600 mil) of daughter board of 8-bit NAND flash. Please refer to Appendix 3 for pin definitions. Before inserting the daughter board of 8-bit NAND flash, be sure to confirm the notch direction of the daughter board (or pin 1 position) and the chip power supply voltage (1.8V or 3.3V). |
10 | Socket (DIP-8) of daughter board of SPI-NAND flash. Before inserting the SPI-NAND flash chip, be sure to confirm the chip notch direction (or pin 1 position) and the chip power supply voltage (1.8V or 3.3V). There is a WSON-8 soldering pad of SPI-NAND flash under the socket, and the DIP-8 socket can be removed and replaced with a WSON-8 packaged SPI-NAND chip. Note that to test frequencies of SPI-NAND flash above 60MHz, please use WSON-8 packaged chips. |
11 | Socket (DIP-24, 600 mil) of daughter board of eMMC. Please refer to Appendix 2 for pin definitions. Before inserting the eMMC daughter board, be sure to confirm the direction of the daughter board notch (or pin 1 position). There is an FGBA-153 soldering pad of eMMC chip under the socket. The DIP-24 socket can be removed and replace with a FBGA-153 packaged eMMC chip. Note that to test speed above DDR52 or HS100, please use FBGA packaged chips. |
12 | Pin-header (10x2 pins, 100 mil) of JTAG interface of Cortex-A55. Please refer to Appendix 1 for pin definitions. Before inserting the JTAG cable, be sure to confirm the position of pin 1. |
13 | Type A socket of USB 2.0. It supports Full/High speeds, supports Host, Device and OTG 1.0. Current limit of VBUS is 1A. |
14 | Micro AB socket of USB 2.0. It supports Full/High speeds, supports Host, Device and OTG 1.0. Current limit of VBUS is 1A. Please note that USB 2.0 Type A and Micro AB sockets share the same USB 2.0 port, and only one of them can be used at a time. |
15 | Type C socket of USB 3.1 Gen1. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
16 | WiFi/Bluetooth (AMPAK AP6256) module. Main chip of the module is Broadcom BCM43456 chip. |
17 | Pin-header (3-pin, 100-mil, 3.3V) of UART0 (serial port of main console). The pin definitions from left to right are GND, RX, and TX. It is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
18 | Samtec differential socket (QSH-020-01-F-D-DP) of CPIO. CPIO is a high-speed (4.8 GB/s) interface for connecting to a peripheral chip. Chip-to-chip (external mode, on board) transfers support a maximum speed of 4.8 GB/s, and die-to-die (internal mode, in a package) transfers support a maximum speed of 9.6 GB/s. Refer to Section 11 for details. |
19 | FFC connector (15 pins, 1.0mm) of MIPI/CSI-RX4 interface. It is compatible with the Raspberry Pi camera FFC connector. Please refer to Appendix 5 for pin definitions. |
20 | FFC connector (24-pin, 0.5mm, top-contact) of MIPI/CSI-RX5. Please refer to Appendix 6 for pin definitions. |
21 | FFC connector (15-pin, 1.0mm) of MIPI/DSI-TX interface. It is compatible with the Raspberry Pi display FFC connector. Please refer to Appendix 7 for pin definitions. |
22 | FFC connector (30-pin, 0.5mm, top-contact) of MIPI/DSI-TX interface. The interface also supports MIPI/CSI-TX functionality. Please refer to Appendix 7 for pin definitions. Please note that both MIPI/DSI-TX connectors (J21 and J22) share the same MIPI/DSI-TX interface and cannot be used at the same time. |
23 | C3V-W chip (15mm x 15mm, 526-pin, TF-BGA). |
24 | Pin-header (2x10, 100mill) of Audio. Please refer to Appendix 4 for pin definitions. |
25 | Pin-header (3-pin, 100-mil, 3.3V) of UART6 (serial port). The pin definitions from top to bottom are GND, RX, and TX. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
26 | Reset key. Reset CM4 and main power-domains, but does not reset RTC. |
27 | Boot configuration switch (SW2) of C3V-W chip. Please refer to Section 3 "Boot Device and Configuration" for boot configuration switch setting. |
28 | Boot configuration switch (SW3) of C3V-W chip. Please refer to Section 3 "Boot Device and Configuration" for boot configuration switch setting. |
29 | Pin-header (2x10 pins, 100 mil) of JTAG interface of Cortex M4. Before inserting the JTAG cable, please be sure to confirm the position of pin 1. Please refer to Appendix 9 for pin definitions. |
30 | Micron LPDDR4 SDRAM (3200Mbps). The C3V-W chip supports three types of DDR SDRAM, including LPDDR4, DDR4 and DDR3, with a maximum size of 8 GiB. |
31 | Pin-headers of 1.8V ←→ 3.3V/3.0V bi-directional voltage-translators. |
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Jumpers | Descriptions | Remarks |
J1, J2, J4, J6, J7, J9, J10, J12, J13, J14, J15 | Pin-headers (4 pins, 100 mil) for measuring current or voltage. |
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J3 | Pin-header (2 pins, 100 mil) for feeding external +12V DC power directly. | No use by default |
J5 | When plug a jumper in J5, the CM4 (AO) domain power supply is controlled by the CM4_PWR_EN signal. | Plug a jumper in |
J8 | When plug a jumper in J8, the VDD_VV (video codec) power is controlled by the VV_PWR_EN signal. | Plug a jumper in when need. |
J11 | When plug a jumper in J11, the VDD_NPU (NPU) power is controlled by the CM4_PWR_EN signal. | Plug a jumper in when need. |
J16, J17, J18, J20 | Pin-headers (2 pins, 100 mil) for control signals of Raspberry Pi camera. |
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J19, J21 | Pin-headers (2 pins, 100 mil) for control signals of “MIPI/DSI-TX to HDMI” daughter board of FORLINX EMBEDDED. |
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J22 | Plug a jumper in J22 to turn on power of SPI-NOR / SPI-NAND (X2) flash forcibly. | No connect by default |
J23 | Plug a jumper in J23 to turn on power of SPI-NAND (X1) flash forcibly. | No connect by default |
J24 ~ J37, J40, J43, J46 | Pin-headers (4 pins, 100 mil) for measuring signals conveniently. |
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J38, J41 | Pin-headers (1 pin) of SYS_1V8 power for supplying external devices. |
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J39, J42 | Pin-headers (1 pin) of SYS_3V power for supplying external devices. |
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J44, J47 | Pin-headers (1 pin) of SYS_3V3 power for supplying external devices. |
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J45, J48 | Pin-header (1 pin) of SYS_5V power for supplying external devices. |
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J49 | Plug a jumper in J49 to turn on power of VBUS of USB 3.0 Type C socket forcibly. | No connect by default |
J50 | Plug a jumper in J50 to turn on power of VBUS of USB 2.0 Micro AB socket forcibly. | No connect by default |
J51 | Pin header (5 pins, 100 mil) of SAR ADC input. The pin definitions from top to bottom are GND, CH3, CH2, CH1, and CH0. |
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J52 | Plug a jumper in J52 to turn on power of VBUS of USB 2.0 Type A socket forcibly. | No connect by default |
J53 | Plug a jumper in J53 to turn on power of SD card forcibly. | No connect by default |
J54 | Pin-header (8 pins, 100 mil) for measuring signals of SD card. |
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J55 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of GPIO50 ~ GPIO59. | Refer to Section 5. |
J60 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of GPIO60 ~ GPIO69. | Refer to Section 5. |
J64 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of GPIO70 ~ GPIO79. | Refer to Section 5. |
J56, J61 | Pin headers (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of boot devices. | Refer to Section 3. |
J73 | Pin header (2 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of boot devices. | Refer to Section 3. |
J57 | Plug a jumper in J57 to activate PER_RESET signal. | Plug a jumper in |
J58, J59, J62, J63, J65 ~ J72 | Pin headers (4 pins, 100 mil) of 1.8V / 3.3V bi-directional voltage translators. | Refer to Section 12. |
J74 | Pin-header (7 pins, 100 mil) for measuring signals of boot configuration switches (SW2 and SW3). |
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J75 | Plug a jumper in J75 to supply power for burning OTP. | Plug a jumper in J75 when burning OTP. |
J76 | Pin header (2 pins, 100 mil) for using the signals. |
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J77 | Pin header (3 pins, 100 mil) for selecting working voltage (1.8V or 3.0V) of VDDIO of AP6256. Please refer to Section 6. | Select DD_DVIO_SDIO |
J78 | Plug a jumper in J78 to turn on power of AP6256 module forcibly. | No connect by default |
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The C3V-W chip supports booting from SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, and SD card. It supports both 1.8V and 3.0V (3.3V) IO voltage for all boot devices.
Please note:
SPI-NAND flash, 8-bit NAND flash and eMMC share pins and cannot be used at the same time (the three chips cannot be mounted on the EVB at the same time).
Please confirm the voltage of chip power supply and configure jumpers correctly. Incorrectly configuring voltage of the chip power supply will cause the chip to burn out.
The following describes configuration method of each boot device.
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Supply voltage of SPI-NOR flash chip | J56 | J73 |
1.8V |  |  |
3.0V |  |  |
3.2 Boot from SPI-NAND flash
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Voltage of VDD_DVIO_2 | J61 |
1.8V | |
3.0V |
5.6 Additional note
Please note that for GPIOs that support dual operation voltage of 1.8V and 3.0V, in addition to configuring the power supply in the hardware, the software also needs to set the MS control bit to get the correct bias voltage.
i-boot will set MS control bit for boot devices if you set jumper J73 correctly.
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