Overview
The aim of this document is to explain how to setup pins of SP7350 in device-tree source. SP7350 has 106 general purpose IO (GPIO) pins which are multiplexed with other special functions, like eMMC device, SPI-NOR flash, SPI-NAND flash, Ethernet PHY (RGMII or RMII interface), UART, I2C pins, and etc.
The following sections will explain how to setup GPIOs and special function pins in device-tree source file. Note that the same device-tree source file is used by U-Boot and Linux in SP7350. Both Pinctrl drivers support generic helper bindings.
Properties
function
The function to be applied on particular pins or groups. See section "Functions" below.
pins
The pins to apply the properties to. See section "Pins" below.
groups
The group to apply the properties to. See section "Groups" below.
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SP7350 has 106 GPIO pins. ID is from 0 to 105. Name is in form of GPIO(id), like GPIO0, GPIO1, GPIO2, GPIO99, GPIO105, and etc. There are two kinds of GPIO pins. One is 1.8V GPIO pins, and the other is 1.8V/3.0V Dual Voltage IO (DVIO) pins. Beside configure 1.8V or 3.0V power to power supply to of a DVIO group in your circuit boards (hardware), you need to setup MS control in device-tree source. Refer to groups of GPIO and DVIO in appendix GPIO Table below for in details.
Groups
We define a bunch of groups as listed in appendix Function-group Table below.
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pinmux
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Here we only list the generic pinmux methods supported by SP7350. |
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This will configure an input pin to run in schmittSchmitt-trigger mode.
argument
The argument is ignored.
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pinconf_example {
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input-schmitt-enable;
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}; |
input-Schmittschmitt-disable
description
This will disable the pin's Schmitt-trigger mode.
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The pin will be pulled up strongly.
| Note |
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For GPIO only, exclude excluding DVIO. |
argument
The argument is ignored.
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That is, GPIO [20, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
GMAC
Pins of GMAC of SP7350, [RXC, RXDV, RXD0, RXD1, RXD2, RXD3, TXC, TXEN, TXD0, TXD1, TXD2, TXD3, MDC, MDIO], can be multiplexed to pin-group GPIO [3, 4, 5, 6, 13, 14, 10, 11, 7, 8, 15, 16, 9, 12] .
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That is, GPIO [3, 4, 5, 6, 13, 14, 10, 11, 7, 8, 15, 16, 9, 12]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
SD Card
Pins of SD card of SP7350, [D1, D0, CLK, CMD, D3, D2], can be multiplexed to pin-group GPIO [38, 39, 40, 41, 42, 43] .
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That is, GPIO [38, 39, 40, 41, 42, 43]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
SDIO
Pins of SDIO of SP7350, [D1, D0, CLK, CMD, D3, D2], can be multiplexed to pin-group GPIO [44, 45, 46, 47, 48, 49] .
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That is, GPIO [44, 45, 46, 47, 48, 49]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
SPI-NOR FLASHFlash
Pins of SPI-NOR FLASH flash of SP7350, [D2, CLK, D1, D3, CSB, D0], can be multiplexed to pin-group GPIO [21, 22, 23, 24, 25, 26] .
To set up pins of SPI-NOR FLASH pinsflash, users need to add properties pinctrl-names and pinctrl-0 to SPI-NOR FLASH flash node spinor@f8000b00 in device-tree source file. For example:
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That is, GPIO [21, 22, 23, 24, 25, 26]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
SPI-NAND FLASHFlash
Pins of SPI-NAND FLASH flash of SP7350, [D0, D2, CLK, D1, D3, CSB], can be multiplexed to pin-group either GPIO [30, 31, 32, 33, 34, 35] .To set up or GPIO [21, 22, 23, 24, 25, 26].
To set up pins of SPI-NAND FLASH pinsflash, users need to add properties pinctrl-names and pinctrl-0 to SPI-NAND FLASH flash node spinand@f8002b80 in device-tree source file. For example:
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String “SPI_NAND_X1” is defined for the pin-group 1 of SPI-NAND FLASH.That is, flash which is mapped to GPIO [30, 31, 32, 33, 34, 35]. See section "Appendix/group_table".
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Users can also use string “SPI_NAND_X2” for the pin-group 2 which is mapped to GPIO [21, 22, 23, 24, 25, 26]. Refer to "Function-group Table" in Appendix.
8-bit NAND FLASH
Pins of 8bit-NAND FLASH of SP7350, [RDY0, WP_B, CE_B, RE_B, CLE, ALE, WE_B, D0, D1, D2, D3, D4, D5, D6, D7], can be multiplexed to pin-group GPIO [20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36] .
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That is, GPIO [20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
UART0
Pins of UART0 of SP7350, [TXD, RXD], can be multiplexed to pin-group GPIO [50, 51] .
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String“UART0_X1” is defined for the pin-group of UART0.
That is, GPIO [50, 51]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
UART1
Pins of UART1 of SP7350, [TXD, RXD, RTS_D, CTS_D], can be multiplexed to pin-group GPIO [52, 53, 54, 55] .
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That is, GPIO [52, 53] and [54, 55]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
I2C0
Pins of I2C0 of SP7350, [CLK, DATA], can be multiplexed to pin-group GPIO [68, 69] .
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String“I2C_COMBO0_X1” is defined for the pin-group of I2C0.
That is, GPIO [68, 69]. See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
PWM
Pins of PWM of SP7350, [PWM_CH0] [PWM_CH1] [PWM_CH2] [PWM_CH3], can be multiplexed to pin-group GPIO [78], [79], [60], [61] .
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String“PWM3_X1” is defined for the pin-group of PWM3. That is, GPIO [61].
See section "Appendix/group_table"Refer to "Function-group Table" in Appendix.
pinconf
One configuration to all pins.
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