...
x (address other than above) // CPU goes to x
Bootstrap pins of SP7350
State of bootstrap pins of SP7350 will be read into bootstrap register (G0.31) at the moment that power-on reset is released. Refer to definition of boot-strap pins of SP7350 below:
Boot-strap pins of SP7350 | Boot devices | |||||||
MX6 | MX5 | MX4 | MX3 | MX2 | MX1 | MX0 | ||
1 | 1 | 1 | 1 | 1 | x | x | eMMC boot | |
1 | 1 | 1 | 0 | 1 | x | x | SPI-NAND boot | |
1 | 1 | 0 | 1 | 1 | x | x | USB boot | |
1 | 1 | 0 | 0 | 1 | x | x | SDC boot | |
1 | 0 | 1 | 1 | 1 | x | x | SPI-NOR | |
1 | 0 | 0 | 0 | 1 | x | x | 8-bit NAND | |
Note:
If MX1 = 0, JTAG interface of CA55 of SP7350 will be enabled.
If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.
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