A built-in ROM code.
Load x-boot image from a boot storage device into SRAM and run it.
Support 6 boot storage devices:
SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card
USB2.0 and USB3.0 flash drives
Support secure-boot.
Support encrypted x-boot.
CPU core 0 is the boot-core and is responsible for booting.
CPU core 1, 2 and 3 spin at i-boot until being waked up.
Support warm-boot (wake up from deep-sleep mode).
CPU core 0 is the boot core.
CPU core 0 is responsible for all boot processes from i-boot to Linux.
CPU core 1, 2 and 3 spin (enter wfe mode) after initialize itself at i-boot.
...
Run Control of CPU Pen (at bootcompat session) :
CPU_WAIT_INIT_VAL (0xffffffff) // CPU waiting (spinning)
CPU_WAIT_A64_VAL (0xfffffffe) // CPU goes to A64
x (address other than above) // CPU goes to x