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The SP7350 incorporates a quad-core ARM Cortex A55 CPU, Verisilicon VIP9000 NPU, Verisilicon video codec, ROM, SRAM, eMMC controller, SPI-NAND flash controller, 8-bit NAND flash controller, UART controller, USB3.0 controller, USB2.0 controller, GPIO, CPIO interface, and DDR3/DDR4/LPDDR4 SDRAM controller, all interconnected by a 128-bit AXI bus, as illustrated in figure below.
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Cortex-A55 x4 (up to 2.1GHz )
L1: 32KiB, L2: 128KiB, L3: 1MiB
Support DVFS (0.7V / 0.8V / 1.0V)
NPU (1GHz@typical case, 4.6 TOPS)
38 AI models, such as yolov5, mobilenet_v2, squeezenet_v1, inception_v3, and etc., have been verified.
Video codec
H.264 encoder (up to 1920x1080 @ 30fps)
H.264 decoder (up to 1920x1080 @ 60fps)
Crypto engine (AES-256, RSA-2048, MD5, GHASH, SHA2/3)
Support DDR3 (1866) / DDR4 (2666) / LPDDR4 (3200), up to 8GiB
4 CH MIPI/CSI-RX (up to 10 virtual channel, 2688x1944)
1 CH MIPI/DSI-TX or MIPI/CSI-TX (1920x1080)
Support 5 boot devices:
SPI-NOR flash
SPI-NAND flash
8-bit NAND flash
eMMC
SD card
DMA / HWRNG / RTC / Watchdog
Cortex-M4 (with dedicated 384 KiB SRAM, run up to 400M)
Support CPIO (chip-to-chip high-speed interface, up to 9.6GB/s)
USB2.0 x1
USB3.1 Gen. 1 x1
Giga Ethernet
SDIO3.0
3 CH I2S audio
4 CH ADC, 4 CH PWM
7 CH UART, 10 CH I2C, 6 CH SPI
9 CH Timer
106 GPIO (including 48 DVIO)
The Cortex A55, designed by ARM, is a 64-bit, quad-core, general-purpose CPU that implements the ARMv8-A instruction set. It provides 31 sets of 64-bit general-purpose registers, a 64-bit program counter, stack pointer, and exception link register. It features L1 cache of 32 KiB each for instructions and data, an L2 cache of 128 KiB, and an L3 cache of 512 KiB. The Cortex A55 supports 64-bit virtual addresses and 48-bit physical addresses, with four privilege modes: unprivileged (EL-0), OS kernel mode (EL-1), Hypervisor mode (EL-2), and monitor mode. It operates in both secure and non-secure worlds.
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The following figure illustrates the operation flow of i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. i-boot loads x-boot from external storage device into SRAM and executes it. x-boot then loads images of TF-A, OP-TEE and U-Boot from external storage device into DRAM and executes TF-A. TF-A runs OP-TEE and then U-Boot, which has already been loaded into DRAM by it. Finally, U-Boot loads Linux from external storage device into DRAM and executes it.
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Ubuntu server and ROS/ROS2 are optional.
Software components after system boots up
Afer system boots up successfully, software components look like figure below. Note that i-boot locates at chip internal mask ROM and is a part of hardware. x-boot, U-Boot only exist temporarily at boot time.
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CPU (Cortex A55) addressing space
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Addressing space for 8 GB DRAM
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Address map of device and regsiters
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