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Software includes i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. The following figure illustrates the operation flow of i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. i-boot loads x-boot from external storage device into SRAM and executes it. x-boot then loads images of TF-A, OP-TEE and U-Boot from external storage device into DRAM and executes TF-A. TF-A runs OP-TEE and then U-Boot, which has already been loaded into DRAM by it. Finally, U-Boot loads Linux from external storage device into DRAM and executes it.
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i-boot
i-boot (internal boot code) is stored in the chip's internal mask ROM. Upon power-on reset, when the system initializes, the program counters of all CPUs (four ARM Cortex A55) are set to point to the entry point address of the i-boot program. Once the power-on reset deasserts, the CPUs start executing from the entry point address of the i-boot program. i-boot first initializes the CPU, sets up all interrupt vectors, initializes the stack, initializes the cache, configures serial ports, sets timers, and more. After initialization, it loads x-boot from external storage devices into SRAM and executes it.
x-boot
x-boot (external boot code) is a first-stage boot-loader placed in eMMC, NAND flash, or SD cards, loaded into system SRAM by i-boot. As it runs on SRAM, its size (including code, data, and stack) must not exceed the system SRAM's capacity. The primary task of x-boot is to initialize the DRAM controller and PHY, perform calibration on DRAM PHY and signals, and once calibrated, the DRAM is ready for use. x-boot then switches the CPU from 32-bit mode to 64-bit mode and loads TF-A and U-Boot from external storage into DRAM, executing TF-A.
TF-A
TF-A (ARM Trusted Firmware-A), developed by ARM, operates at the highest privilege level (EL-3) under ARMv8-A, providing APIs for switching between the secure world and non-secure world. After TF-A completes initialization, it jumps to execute U-Boot (already loaded into DRAM by x-boot).
OP-TEE (Open Portable Trusted Execution Environment)
OP-TEE is an open-source.
U-Boot
U-Boot (Universal Boot-loader), developed by Denx Software Engineering, serves as the second-stage bootloader in this system. U-Boot is widely used in embedded systems, supporting various computer architectures. It is free software under the GNU General Public License. As it runs in DRAM, its size is no longer limited by SRAM (only limited by the system's DRAM size), ranging from hundreds of kilobytes to several megabytes. Apart from being a bootloader for the Linux kernel, U-Boot supports access to storage devices like USB flash drives, SD cards, hard disks, reads and burns NOR flash, NAND flash, and eMMC, and supports file systems such as FAT, ext2, ext3, ext4, nfs, ubifs. It also supports network protocols and functions like Ethernet, DHCP, BOOTP, TFTP, NFS, among many others. After initializing itself and external devices, U-Boot then loads Linux from external storage into DRAM and executes it.
Linux
Linux is an open-source Unix-like operating system. Linus Torvalds first released its kernel on October 5, 1991. Combined with other utilities, Linux has become a complete operating system. It supports various computer architectures, and anyone can freely use, modify, and redistribute it as long as they adhere to the GNU General Public License. Linux manages all devices on the system, including the CPU, interrupt controller, timer, and DRAM, while all applications run under its management.
FreeRTOS
The following figure illustrates the operation flow of i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. i-boot loads x-boot from external storage device into SRAM and executes it. x-boot then loads images of TF-A, OP-TEE and U-Boot from external storage device into DRAM and executes TF-A. TF-A runs OP-TEE and then U-Boot, which has already been loaded into DRAM by it. Finally, U-Boot loads Linux from external storage device into DRAM and executes it.
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FreeRTOS is an open-source.
Note that i-boot locates at chip internal mask ROM and is a part of hardware. x-boot, U-Boot only exist temporarily at boot time. Ubuntu server and ROS/ROS2 are optional.
Software components after system boots up
Afer system boots up successfully, software components stacked look like figure below. Note that i-boot locates at chip internal mask ROM and is a part of hardware. x-boot, U-Boot only exist temporarily at boot time.
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CPU (Cortex A55) addressing space
This project's hardware supports a CPU of SP7350 supports 16 GiB address addressing space (with 34 address lines), including 8 GiB for the C chip DRAM and 4 GiB each reserved for CPIO-L and CPIO-R. The address layout of the addressing space layout is depicted in Figure 2.1:In 3 figures below: One is for 2 GiB DRAM, another is for 4 GiB DRAM, and the other is for 8 GiB DRAM. Let explain below sections.
Addressing space for 2 GB DRAM
Refer to figure below, in the first 4 GiB address space, the initial 3.5 2 GiB is allocated for the C chip's DRAM, while the remaining 0.5 25 GiB is reserved for chip internal C chip devices and registers. The second and the forth 4 GiB address space is dedicated to the C chip's DRAMare reserved (no use). The third 4 GiB address space is reserved for the device (or P-chip) which is connected to CPIO-L, and the fourth with CPIO bus.
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Addressing space for 4 GB DRAM
Refer to figure below, the first 0.75 GiB address space isallocated for the DRAM, followed by 0.25 GiB address space for chip internal devices and registers. The initial 0.25 GiB of the second 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use). The third 4 GiB address space is for the device (or P-chip) which is connected to with CPIO -Rbus. The C chip has a total of 8 GiB of address space, and each of the two P chips has a 4 GiB address space.
Addressing space for 2 GB DRAM
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Addressing space for 4 GB DRAM
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last 4 GiB address space is reserved (no use).
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Addressing space for 8 GB DRAM
Refer to figure below, the first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for the DRAM. The third 4 GiB address space is for the device (or P-chip) which is connected with CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use).
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Address map of device and registers
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