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Under construction…

A built-in ROM code.

Load x-boot image from a boot storage device into SRAM and run it.

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Support warm-boot (wake up from deep-sleep mode).

Features of

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i-

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boot

  1. Output log at UART0 at 115,200 bps.

  2. UART0 pins can be turned off by OTP bit.

  3. Read IV_MX[6..3] pins to decide boot-device.

  4. Support boot-devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, USB flash drive

  5. Support secure-boot.

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  1. Secure-boot is enabled by OTP bit.

  2. Support warm-boot.

  3. Support peripheral-reset signal (output from G_MX2).

Drivers

Features

8-bit NAND

  1. Support loading x-boot image from 8-bit NAND flash.

  2. First block of 8-bit NAND flash should contain Sunplus Boot Profile Header.

  3. Support reading 1K60 ECC sectors.

  4. x-boot image should be stored in 1K60 ECC sectors.

  5. Set MS control of pins of 8-bit NAND flash.

  6. Read cycle-time is 240 nS.

eMMC

  1. Load x-boot image from eMMC device.

  2. x-boot image should be stored at Boot Area Partition 1.

  3. Set MS control of pins of eMMC device.

  4. Bus clock is 25 MHz.

SPI-NAND

  1. Support loading x-boot image from SPI-NAND flash.

  2. First block of SPI-NAND flash should contain Sunplus Boot Profile Header.

  3. Support reading 1K60 ECC sectors.

  4. x-boot image should be stored in 1K60 ECC sectors.

  5. Support X1 and X2 position of SPI-NAND.

  6. Set MS control-bit of pins of SPI-NAND flash.

  7. Bus clock is 11.2 MHz.

SD card

  1. Support loading x-boot image from an SD card.

  2. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  3. File ISPBOOOT.BIN should be stored root directory of first partition of the SD card.

  4. First partition of the SD card should be FAT32 or FAT16 format.

  5. Bus clock is 5 MHz.

USB2.0 Host

  1. Support loading x-boot image from an USB flash drive in USB2.0 port.

  2. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  3. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  4. First partition of the USB flash drive should be FAT32 or FAT16 format.

  5. Support high-speed read operation only

USB3.0 Host

  1. Support loading x-boot image from an USB flash drive in USB3.0 port.

  2. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  3. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  4. First partition of the USB flash drive should be FAT32 or FAT16 format.

  5. Support high-speed read operation only

Boot core and others

CPU core 0 is the boot core.

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CPU core 1, 2 and 3 spin (enter wfe mode) after initialize itself at i-boot.

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image-20240122-034050.png

Run Control of CPU Pen (at bootcompat session) :

image-20240122-034202.png

CPU_WAIT_INIT_VAL (0xffffffff)    // CPU waiting (spinning)

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x (address other than above)    // CPU goes to x

Bootstrap pins of SP7350

State of bootstrap pins of SP7350 will be read into bootstrap register (G0.31) at the moment that power-on reset is released. Refer to definition of boot-strap pins of SP7350 below:

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