This article provides a brief overview of the SP7350 software. Subsequent articles will delve into the detailed components of the software. The initial section begins with an introduction to the basic hardware through block diagrams, followed by an explanation of software operations. The final will touch upon CPU addressing space and register addresses.
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Hardware
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introduction
The SP7350 incorporates a quad-core ARM Cortex A55 CPU, Verisilicon VIP9000 NPU, Verisilicon video codec, ROM, SRAM, eMMC controller, SPI-NAND flash controller, 8-bit NAND flash controller, UART controller, USB3.0 controller, USB2.0 controller, GPIO, CPIO interface, and DDR3/DDR4/LPDDR4 SDRAM controller, all interconnected by a 128-bit AXI bus, as illustrated in figure below.
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The maximum supported capacity of DRAM is 8 GiB. The P chip is designed by the customer to include specific peripherals such as Giga Ethernet, USB3.1 Gen 2, Image fusion processor, MIPI CSI-2, WiFi, Display Engine, and etc. The C chip provides powerful computation capabilities, including general computation, AI inference, graphic computation, and video compression/decompression, meeting the customer's computation needs.
Software
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operations
Software includes i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. i-boot (internal boot code) is stored in the chip's internal mask ROM. Upon power-on reset, when the system initializes, the program counters of all CPUs (four ARM Cortex A55) are set to point to the entry point address of the i-boot program. Once the power-on reset deasserts, the CPUs start executing from the entry point address of the i-boot program. i-boot first initializes the CPU, sets up all interrupt vectors, initializes the stack, initializes the cache, configures serial ports, sets timers, and more. After initialization, it loads x-boot from external storage devices into SRAM and executes it.
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