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The SP7350 incorporates a quad-core ARM Cortex A55 CPU, Verisilicon VIP9000 NPU, Verisilicon video codec, ROM, SRAM, eMMC controller, SPI-NAND flash controller, 8-bit NAND flash controller, UART controller, USB3.0 controller, USB2.0 controller, GPIO, CPIO interface, and DDR3/DDR4/LPDDR4 SDRAM controller, all interconnected by a 128-bit AXI bus, as illustrated in figure below.
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Cortex-A55 x4 (up to 2.1GHz )
L1: 32KiB, L2: 128KiB, L3: 1MiB
Support DVFS (0.7V / 0.8V / 1.0V)
NPU (1GHz@typical case, 4.6 TOPS)
38 AI models, such as yolov5, mobilenet_v2, squeezenet_v1, inception_v3, and etc., have been verified.
Video codec
H.264 encoder (up to 1920x1080 @ 30fps)
H.264 decoder (up to 1920x1080 @ 60fps)
Crypto engine (AES-256, RSA-2048, MD5, GHASH, SHA2/3)
Support DDR3 (1866) / DDR4 (2666) / LPDDR4 (3200), up to 8GiB
4 CH MIPI/CSI-RX (up to 10 virtual channel, 2688x1944)
1 CH MIPI/DSI-TX or MIPI/CSI-TX (1920x1080)
Support 5 boot devices:
SPI-NOR flash
SPI-NAND flash
8-bit NAND flash
eMMC
SD card
DMA / HWRNG / RTC / Watchdog
Cortex-M4 (with dedicated 384 KiB SRAM, run up to 400M)
Support CPIO (chip-to-chip high-speed interface, up to 9.6GB/s)
USB2.0 x1
USB3.1 Gen. 1 x1
Giga Ethernet
SDIO3.0
3 CH I2S audio
4 CH ADC, 4 CH PWM
7 CH UART, 10 CH I2C, 6 CH SPI
9 CH Timer
106 GPIO (including 48 DVIO)
The Cortex A55, designed by ARM, is a 64-bit, quad-core, general-purpose CPU that implements the ARMv8-A instruction set. It provides 31 sets of 64-bit general-purpose registers, a 64-bit program counter, stack pointer, and exception link register. It features L1 cache of 32 KiB each for instructions and data, an L2 cache of 128 KiB, and an L3 cache of 512 KiB. The Cortex A55 supports 64-bit virtual addresses and 48-bit physical addresses, with four privilege modes: unprivileged (EL-0), OS kernel mode (EL-1), Hypervisor mode (EL-2), and monitor mode. It operates in both secure and non-secure worlds.
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CPU (Cortex A55) addressing space
This project's hardware supports a 16 GiB address space (with 34 address lines), including 8 GiB for the C chip and 4 GiB each reserved for CPIO-L and CPIO-R. The address space layout is depicted in Figure 2.1:
In the first 4 GiB address space, the initial 3.5 GiB is allocated for the C chip's DRAM, while the remaining 0.5 GiB is reserved for internal C chip devices. The second 4 GiB address space is dedicated to the C chip's DRAM. The third 4 GiB space is reserved for the P chip connected to CPIO-L, and the fourth 4 GiB address space is reserved for the P chip connected to CPIO-R. The C chip has a total of 8 GiB of address space, and each of the two P chips has a 4 GiB address space.
Addressing space for 2 GB DRAM
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Addressing space for 8 GB DRAM
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Address map of device and registers
The following figure provides a detailed view of the address map, starting from address 0xf0000000. It begins with 64 MiB of SPI-NOR flash (direct address space for NOR flash), followed by 64 MiB of SPI-NAND flash (direct address space for NAND flash), 8 MiB of device
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registers (such as UART controller, RTC controller, OTP controller, SPI-NOR flash controller, SPI-NAND flash controller, eMMC controller, SD card controller, USB3 controller, etc.), 4 MiB of AO registers, 16 MiB of DDR controller registers, 1 MiB of Cortex-A55 (4-core CPU) registers, 1 MiB of Cortex-M4 (micro-controller) registers, 256 KiB of CBDMA SRAM, 384 KiB of CM4 SRAM, 64 MiB 8-bit NAND flash controller and 96 KiB of ROM.
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