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CPU (Cortex A55) addressing space
The CPU of SP7350 supports a 16 GiB addressing space (with 34 address lines), including 8 GiB for DRAM and 4 GiB reserved for CPIO. The layout of the addressing space layout is depicted in 3 three figures below: One is for 2 GiB DRAM, another is for 4 GiB DRAM, and the other is for 8 GiB DRAM. Let explain below sections.
Addressing
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Space for 2 GB DRAM
Refer to figure below, in In the first 4 GiB address space, the initial 2 GiB is allocated for the DRAM, while the remaining 0.25 GiB is reserved for chip internal devices and registers. The second and the forth fourth 4 GiB address space spaces are reserved (no use). The third , and the third 4 GiB address space is for the device (or P-chip) which is connected with the CPIO bus.
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Addressing space for 4 GB DRAM
Refer to figure below, the The first 0.75 GiB address space isallocated is allocated for the DRAM, followed by 0.25 GiB address space for chip internal devices and registers. The initial 0.25 GiB of the second 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use). The third 4 GiB address space is for the device (or P-chip) which is connected with the CPIO bus. The , and the last 4 GiB address space is reserved (no use).
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Addressing space for 8 GB DRAM
Refer to figure below, the The first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for DRAM, and the DRAM. The third 4 GiB address space is for the device (or P-chip) which is connected with the CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use).
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Address map of devices and registers
The following figure provides a detailed view of the address map , starting from begins at address 0xf0000000. It begins with includes segments such as 64 MiB of SPI-NOR flash (direct address space for NOR flash), followed by 64 MiB of SPI-NAND flash (direct address space for SPI-NAND flash), 8 MiB of device registers (such as OTP controller, SPI-NOR flash controller, SPI-NAND flash controller, eMMC controller, SD card controller, USB3 controller, etc.), 4 MiB of AO device registers (such as UART controller, RTC controller, I2C, SPI and etc.), 16 MiB of DDR SRAM controller registers, 1 MiB of Cortex-A55 registers, 1 MiB of Cortex-M4 registers, 256 KiB of CBDMA SRAM, 384 KiB of CM4 SRAM, 64 MiB 8-bit NAND flash controller, and 96 KiB of ROM.
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