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i-boot (internal boot code) is , stored in the chip's internal mask ROM. Upon , plays a crucial role in the system's initialization process. During power-on reset, when the system initializes, the program counters of all CPUs ( four ARM Cortex A55 ) CPUs are set configured to point to the entry point address of the i-boot program. Once Upon the completion of power-on reset deasserts, the CPUs start executing commence execution from the this entry point address of the i-boot program. i-boot first initializes the CPU, sets up all undertakes a series of essential tasks, including CPU initialization, setting up interrupt vectors, initializes the stack initialization, initializes the cache setup, configures serial ports, sets timersport configuration, timer configuration, and more. After

Following this initialization phase, it i-boot loads x-boot from external storage devices into SRAM and executes itperforms a checksum verification. If the verification passes, i-boot proceeds to execute x-boot.

Table of Contents

Features

Key features of i-boot

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  1. Output log at UART0 at with a baud rate of 115,200 bps.

  2. UART0 pins can be turned off by through an OTP bit.

  3. Read bootstrap pins IV_MX[6..3] pins to decide boot-device.

  4. Support 5 for five boot - devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, and USB flash drive (on either USB2.0 or USB3.0 port).

  5. Support Implementation of secure-boot .

    Verify

    with the ability to verify the digital signature of the x-boot image and decrypt it.

  6. Decrypt x-boot image.

  7. Secure-boot is enabled activation controlled by an OTP bit.

  8. Support for warm-boot (, enabling wake-up from deep-sleep mode).

  9. Support for the peripheral-reset signal (output from G_MX2).

Main flow

The i-boot flow initiates with the reset vector, followed by the execution of the "cpu_init" subroutine responsible for initializing the CPU. Next in the sequence is the "start_boot" subroutine, which sets up the C execution environment. The flow then advances to execute the "iboot_main" subroutine, serving as the C main function within i-boot.

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The "iboot_main" subroutine commences by invoking the "init_cdata" subroutine to initialize global C data. It then proceeds to read boot-strap pins from a dedicated hardware register, storing the information in the C structure "g_bootinfo". In the event of a warm-boot scenario, it checks the readiness of DRAM (where CM4 handles the restoration of DDR IO retention data and specific hardware registers or settings). If DRAM is confirmed ready, the subroutine redirects to the start address of the warm-boot module to continue the warm-boot processes.

In cases where a warm-boot is not applicable (in cold-start scenario), the process continues to execute the "AV1_STC_init()", "init_uart()", and "init_hw()" subroutines to initialize hardware components. Finally, it advances to run the "boot_flow()" subroutine.

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image-20240125-054245.png

Device drivers

Drivers

Features

8-bit NAND

  1. First block of 8-bit NAND flash should contain Sunplus Boot Profile Header.

  2. Support reading 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Set MS control of pins of 8-bit NAND flash.

  5. Read cycle-time is 240 nS.

eMMC

  1. x-boot image should be stored at Boot Area Partition 1.

  2. Set MS control of pins of eMMC device.

  3. Bus clock is 25 MHz.

SPI-NAND

  1. First block of SPI-NAND flash should contain Sunplus Boot Profile Header.

  2. Support reading 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Support X1 and X2 position of SPI-NAND.

  5. Set MS control-bit of pins of SPI-NAND flash.

  6. Bus clock is 11.2 MHz.

SD card

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. File ISPBOOOT.BIN should be stored root directory of first partition of the SD card.

  3. First partition of the SD card should be FAT32 or FAT16 format.

  4. Bus clock is 5 MHz.

USB2.0 Host

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  3. First partition of the USB flash drive should be FAT32 or FAT16 format.

  4. Support high-speed read operation only

USB3.0 Host

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  3. First partition of the USB flash drive should be FAT32 or FAT16 format.

  4. Support high-speed read operation only

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CPU core 0 is the boot core and is responsible for booting. It is responsible for all boot processes from i-boot to Linux. CPU core 1, 2 and 3 spin (enter wfe mode) after initializing itself until core 0 wake up them.

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image-20240122-034050.png

Run Control of CPU

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(at bootcompat session) :

image-20240122-034202.png

CPU_WAIT_INIT_VAL (0xffffffff)    // CPU waiting (spinning)

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