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It's essential to note that i-boot does not initialize DDR DRAM, rendering it temporarily unavailable. Hence, x-boot must be loaded into SRAM for execution.
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Boot devices
i-boot Boot supports for 5 five boot devices. The following table lists the specifications or requirements of , each with specific specifications and requirements. Below is a detailed table outlining the specifications for each boot device:
Boot devices | Specifications |
8-bit NAND flash | First block of 8-bit NAND flash The first block should contain Sunplus Boot Profile Header. x-boot image should be stored in 1K60 ECC sectors. x-boot image should be stored in 1K60 ECC sectors. Read Set read cycle-time is set to 240 nS. GPIO82 should be set to HIGH if for 3.0V NAND flash is used or , LOW if for 1.8V NAND flash is used.
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eMMC device | x-boot image should be stored at Boot Area Partition 1. Bus Set bus clock is set to 25 MHz. GPIO82 should be set to HIGH if for 3.0V IO power is used or , LOW if for 1.8V IO power is used.
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SPI-NAND flash | First block of SPI-NAND flash should contain Sunplus Boot Profile Header. x-boot image should be stored in 1K60 ECC sectors. Support for X1 and X2 position of SPI-NAND. First try positions. Attempt X1 position first and then proceed to X2 position. Bus Set bus clock is set to 11.2 MHz. GPIO82 should be set to HIGH if for 3.0V SPI-NAND flash is used or , LOW if for 1.8V SPI-NAND flash is used.
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SPI-NOR flash | x-boot image should be stored at offset 0x18000 (96Ki96KiB). Bus Set bus clock is set to 11.2 MHz. GPIO82 should be set to HIGH if for 3.0V SPI-NOR flash is used or , LOW if for 1.8V SPI-NOR flash is used.
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SD card | x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN. The file ISPBOOOT.BIN should be stored in the root directory of the first or sole partition of the SD card. First or sole partition of the SD card The partition should be formatted to FAT32 or FAT16 formatfile-system. Bus Set bus clock is set to 5 MHz.
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USB flash drive | x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN. The file ISPBOOOT.BIN should be stored in the root directory of first or sole partition of the USB flash drive.First or sole partition of the USB flash drive The partition should be formatted to FAT32 or FAT16 formatfile-system. Support high-speed read operation only Support USB flash drive on both USB2.0 or USB3.0 ports. Try Attempt USB3.0 port first and then proceed to USB2.0 port.
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Boot core and other cores
CPU core 0 is serves as the boot core and is responsible for booting. It is , responsible for all boot processes from i-boot to Linux. Meanwhile, CPU core 1, 2, and 3 enter a spin state (enter wfe mode) inside i-boot after initializing itself until core 0 wake up them.
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initialize itself, awaiting activation by core 0. The following assembly shows the processes.
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Run Control of CPU (at bootcompat session) :
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x (address other than above) // CPU goes to x
Bootstrap pins of SP7350
State The state of bootstrap pins of SP7350 will be is read into bootstrap register (G0.31) at the moment that upon releasing power-on reset is released. Refer to definition of boot-strap pins of SP7350 in i-boot below:
Boot-strap pins of SP7350 | Boot devices |
MX6 | MX5 | MX4 | MX3 | MX2 | MX1 | MX0 |
1 | 1 | 1 | 1 | 1 | x | x | eMMC boot |
1 | 1 | 1 | 0 | 1 | x | x | SPI-NAND boot |
1 | 1 | 0 | 1 | 1 | x | x | USB boot |
1 | 1 | 0 | 0 | 1 | x | x | SDC boot |
1 | 0 | 1 | 1 | 1 | x | x | SPI-NOR boot |
1 | 0 | 0 | 0 | 1 | x | x | 8-bit NAND boot |
Note:
If MX1 = 0, the JTAG interface of CA55 of SP7350 will be enabled.
If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.
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