This article provides a brief overview of the SP7350 software. Subsequent articles will delve into the detailed components of the software. The initial section begins with an introduction to the basic hardware through block diagramssoftware operations, followed by an explanation of software operationsCPU addressing space. The final will touch upon CPU addressing space and register addresses.
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Hardware introduction
The SP7350 incorporates a quad-core ARM Cortex A55 CPU, Verisilicon VIP9000 NPU, Verisilicon video codec, ROM, SRAM, eMMC controller, SPI-NAND flash controller, 8-bit NAND flash controller, UART controller, USB3.0 controller, USB2.0 controller, GPIO, CPIO interface, and DDR3/DDR4/LPDDR4 SDRAM controller, all interconnected by a 128-bit AXI bus, as illustrated in figure below.
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Cortex-A55 x4 (up to 2.1GHz )
L1: 32KiB, L2: 128KiB, L3: 1MiB
Support DVFS (0.7V / 0.8V / 1.0V)
NPU (1GHz@typical case, 4.6 TOPS)
38 AI models, such as yolov5, mobilenet_v2, squeezenet_v1, inception_v3, and etc., have been verified.
Video codec
H.264 encoder (up to 1920x1080 @ 30fps)
H.264 decoder (up to 1920x1080 @ 60fps)
Crypto engine (AES-256, RSA-2048, MD5, GHASH, SHA2/3)
Support DDR3 (1866) / DDR4 (2666) / LPDDR4 (3200), up to 8GiB
4 CH MIPI/CSI-RX (up to 10 virtual channel, 2688x1944)
1 CH MIPI/DSI-TX or MIPI/CSI-TX (1920x1080)
Support 5 boot devices:
SPI-NOR flash
SPI-NAND flash
8-bit NAND flash
eMMC
SD card
DMA / HWRNG / RTC / Watchdog
Cortex-M4 (with dedicated 384 KiB SRAM, run up to 400M)
Support CPIO (chip-to-chip high-speed interface, up to 9.6GB/s)
USB2.0 x1
USB3.1 Gen. 1 x1
Giga Ethernet
SDIO3.0
3 CH I2S audio
4 CH ADC, 4 CH PWM
7 CH UART, 10 CH I2C, 6 CH SPI
9 CH Timer
106 GPIO (including 48 DVIO)
The Cortex A55, designed by ARM, is a 64-bit, quad-core, general-purpose CPU that implements the ARMv8-A instruction set. It provides 31 sets of 64-bit general-purpose registers, a 64-bit program counter, stack pointer, and exception link register. It features L1 cache of 32 KiB each for instructions and data, an L2 cache of 128 KiB, and an L3 cache of 512 KiB. The Cortex A55 supports 64-bit virtual addresses and 48-bit physical addresses, with four privilege modes: unprivileged (EL-0), OS kernel mode (EL-1), Hypervisor mode (EL-2), and monitor mode. It operates in both secure and non-secure worlds.
The VIP9000 NPU, designed by Verisilicon, is a Neural-network Processor Unit (NPU) specialized for hardware-accelerated processing in artificial intelligence, particularly in neural networks, machine vision, and machine learning. It includes 2048 MACs and achieves computational performance up to 5 TOPS (@900MGHz). Verisilicon provides development environments like AcuityIDE, enabling developers to easily create AI programs and applications.
The DDR3/DDR4/LPDDR4 SDRAM controller, designed by Synopsys, supports three types of DRAM: DDR3, DDR4, and LPDDR4. It features 2 channels, each with 16 bits, totaling 32 bits. The maximum capacity of DRAM supported is 8 GiB, with a maximum speed of 12.8 GiB/s (@1600MHz).
The ROM has a size of 96 KiB and stores the boot program. The first instruction executed after CPU reset resides in the ROM, responsible for initializing the system and loading the next stage of the boot loader from storage devices and executing it. The SRAM has a size of 256 KiB, serving as high-speed RAM for the system or a buffer for DMA transfers. In this system, SRAM also has a special purpose as the RAM for loading and executing the boot loader before initializing DRAM.
The eMMC controller supports eMMC specification version 4.41, with a voltage range of 1.8V (SDR 200 MHz) to 3.3V (DDR 52MHz). The SPI-NAND flash controller and 8-bit NAND flash controller support automatic BCH (1K60) and SLC NAND, with a speed of 104 MHz at 3.3V and 133 MHz or STR mode at 1.8V. The SD card controller supports SD 3.0 specification (also known as SDXC), with a maximum capacity of 2 TB, a maximum speed of 104 MB/s, and automatic switching between 3.3V and 1.8V.
The USB3.0 controller, designed by Synopsys, support dual-roll device (DRD) with a maximum transfer capability of 5 Gbps. USB2.0 controller supports host, device and OTG mode. It supports high-speed, full-speed and low-speed mode. The UART controller has 7 channels, and there are 106 GPIO pins supporting multiplexing.
The CPIO, designed by Sunplus, is a high-speed, full-duplex interface for communicating from chiplet to chiplet, supporting 4 lanes for TX/RX data, CPI, and CPI-X modes, supporting data swap, and achieving a transfer capability of 9.6 GiB/s (@4 lanes, 12nm) or 4.8 GiB/s (@4 lanes, 28nm).
The P chip (Peripheral chip), designed by the customer, includes specific peripheral devices according to the customer's requirements. The C chip can connect to one DRAM and one P chip, as shown in figure below:
The maximum supported capacity of DRAM is 8 GiB. The P chip is designed by the customer to include specific peripherals such as Giga Ethernet, USB3.1 Gen 2, Image fusion processor, MIPI CSI-2, WiFi, Display Engine, and etc. The C chip provides powerful computation capabilities, including general computation, AI inference, graphic computation, and video compression/decompression, meeting the customer's computation needs.
device address map.
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Software operations
Software includes i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. The following figure illustrates the operation flow of i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux and FreeRTOS. At power on, i-boot loads x-boot image from external storage device into SRAM, verify and executes it. x-boot first initializes SDRAM controller and trains SDRAM PHY. It then loads images of TF-A, OP-TEE and U-Boot from external storage device into DRAM and verify. Finally, it executes TF-A. TF-A runs invokes OP-TEE and then run U-Boot, which has already been loaded into DRAM by it. Finally, U-Boot loads Linux image from external storage device into DRAM and executes it. After Linux boots up successfully, it loads firmware of CM4 (FreeRTOS) and then starts CM4.
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Note that i-boot locates at chip internal mask ROM and is a part of hardware. x-boot, U-Boot only exist temporarily at boot time. Ubuntu server and ROS/ROS2 are optional. Afer system boots up successfully, software components stacked look like figure below.
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Refer to figure below, the first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for the DRAM. The third 4 GiB address space is for the device (or P-chip) which is connected with CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for the DRAM, while the remaining 3.75 GiB is reserved (no use).
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Address map of
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devices and registers
The following figure provides a detailed view of the address map, starting from address 0xf0000000. It begins with 64 MiB of SPI-NOR flash (direct address space for NOR flash), followed by 64 MiB of SPI-NAND flash (direct address space for SPI-NAND flash), 8 MiB of device registers (such as UART controller, RTC controller, OTP controller, SPI-NOR flash controller, SPI-NAND flash controller, eMMC controller, SD card controller, USB3 controller, etc.), 4 MiB of AO device registers (such as UART controller, RTC controller, I2C, SPI and etc.), 16 MiB of DDR SRAM controller registers, 1 MiB of Cortex-A55 (4-core CPU) registers, 1 MiB of Cortex-M4 (micro-controller) registers, 256 KiB of CBDMA SRAM, 384 KiB of CM4 SRAM, 64 MiB 8-bit NAND flash controller and 96 KiB of ROM.
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