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The "iboot_main" subroutine commences by invoking the "init_cdata" subroutine to initialize global C data. It then proceeds to read boot-strap pins from a dedicated hardware register, storing the information in the C structure "g_bootinfo". In the event of a warm-boot scenario, it checks the readiness of DRAM (where CM4 handles the restoration of DDR IO retention data and specific hardware registers or settings). If DRAM is confirmed ready, the subroutine redirects to the start address of the warm-boot module to continue the warm-boot processes.

In cases where a warm-boot is not applicable (in cold-start scenario), the process continues to execute the "AV1_STC_init()", "init_uart()", and "init_hw()" subroutines to initialize hardware components. Finally, it advances to run the "boot_flow()" subroutine.

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The "boot_flow()" subroutine begins by examining the C structure g_bootinfo to determine the preferred boot device: eMMC, SPI-NAND flash, 8-bit NAND flash, SD card, or USB flash drive. It then initializes the controller of the selected boot device and loads the x-boot image into SRAM from the chosen source. After loading, the subroutine checks the image checksum. If the checksum passes verification, it proceeds to execute x-boot.

In the case of secure-boot activation through OTP bits, the subroutine additionally checks the digital signature and decrypts the image after the checksum validation.

It's essential to note that i-boot does not initialize DDR DRAM, rendering it temporarily unavailable. Hence, x-boot must be loaded into SRAM for execution.

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Device drivers

Drivers

Features

8-bit NAND

  1. First block of 8-bit NAND flash should contain Sunplus Boot Profile Header.

  2. Support reading 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Set MS control of pins of 8-bit NAND flash.

  5. Read cycle-time is 240 nS.

eMMC

  1. x-boot image should be stored at Boot Area Partition 1.

  2. Set MS control of pins of eMMC device.

  3. Bus clock is 25 MHz.

SPI-NAND

  1. First block of SPI-NAND flash should contain Sunplus Boot Profile Header.

  2. Support reading 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Support X1 and X2 position of SPI-NAND.

  5. Set MS control-bit of pins of SPI-NAND flash.

  6. Bus clock is 11.2 MHz.

SD card

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. File ISPBOOOT.BIN should be stored root directory of first partition of the SD card.

  3. First partition of the SD card should be FAT32 or FAT16 format.

  4. Bus clock is 5 MHz.

USB2.0 Host

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  3. First partition of the USB flash drive should be FAT32 or FAT16 format.

  4. Support high-speed read operation only

USB3.0 Host

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. File ISPBOOOT.BIN should be stored root directory of first partition of the USB flash drive.

  3. First partition of the USB flash drive should be FAT32 or FAT16 format.

  4. Support high-speed read operation only

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