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Boot devices

Specifications

8-bit NAND

flash

  1. The first block should contain Sunplus Boot Profile Header.

  2. x-boot image should be stored in 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Set read cycle-time to 240 nS.

  5. GPIO82 set to HIGH for 3.0V NAND flash, LOW for 1.8V NAND flash.

eMMC device

  1. x-boot image should be stored at Boot Area Partition 1.

  2. Set bus clock to 25 MHz.

  3. GPIO82 set to HIGH for 3.0V IO power, LOW for 1.8V IO power.

SPI-NAND flash

  1. First block should contain Sunplus Boot Profile Header.

  2. x-boot image should be stored in 1K60 ECC sectors.

  3. Support for X1 and X2 positions. Attempt X1 position first and then proceed to X2 position.

  4. Set bus clock to 11.2 MHz.

  5. GPIO82 set to HIGH for 3.0V SPI-NAND flash, LOW for 1.8V SPI-NAND flash.

SPI-NOR flash

  1. x-boot image should be stored at offset 0x18000 (96KiB).

  2. Set bus clock to 11.2 MHz.

  3. GPIO82 set to HIGH for 3.0V SPI-NOR flash, LOW for 1.8V SPI-NOR.

SD card

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. ISPBOOOT.BIN should be stored in the root directory of the first or sole partition of the SD card.

  3. The partition should be formatted to FAT32 or FAT16 file-system.

  4. Set bus clock to 5 MHz.

USB flash drive

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. ISPBOOOT.BIN should be stored in the root directory of first or sole partition of the USB flash drive.

  3. The partition should be formatted to FAT32 or FAT16 file-system.

  4. Support high-speed only

  5. Support USB flash drive on both USB2.0 or USB3.0 ports. Attempt USB3.0 port first and then proceed to USB2.0 port.

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CPU boot core and other cores

CPU core 0 serves as the boot core, responsible for all boot processes from i-boot to Linux. Meanwhile, CPU core 1, 2, and 3 enter a spin state (wfe mode) inside within i-boot after initialize itselfself-initialization, awaiting activation by core 0. The following assembly shows the processes.

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Run Control of CPU (at bootcompat session) :

image-20240122-034202.pngImage Removedsubsequent assembly code illustrates these processes.

Line 75~78: Read MPIDR to retrieve the CPU core id.

Line 79 ~ 80: Verify whether the core id is equal to 0 (indicating core 0). If ture, execute the jump to start_boot; otherwise (for core 1, 2, 3), proceed to A_cpu_wait.

Line 84 ~ 99: Retrieve the CPU Run Control field. If the field is equivalent to CPU_WAIT_INIT_VAL, continue a loop (spin) between line 91 ~ 96 (depicted by the red rectangle). If the field is equal to CPU_WAIT_A64_VAL, initiate a jump to A_go_AA_64 (line105). For any other field values, perform a jump to the specified address.

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Each CPU core possesses its own CPU Run Control field, with each field being 32 bits wide and situated in SRAM.

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The values of the CPU Run Control field are defined in the table below:

Values

Define

Descriptions

0xFFFFFFFF

CPU_WAIT_INIT_VAL

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CPU continues spining (waiting)

0xFFFFFFFE

CPU_WAIT_A64_VAL

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CPU goes to

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switch to 64-bit mode.

X

CPU jumps to address X directly.

CPU core 0 fills the specified value into the CPU Run Control field of the target core to wake it up.

Bootstrap pins of SP7350

The state of bootstrap pins of SP7350 is read into bootstrap register (G0.31) upon releasing power-on reset. Refer to definition of boot-strap pins in i-boot below:

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