x-boot (external boot code) is a serves as the first-stage boot-loader placed in , residing in storage devices such as eMMC, NAND flash, or SD cards, . It is loaded into the system SRAM by i-boot, as DRAM is not yet ready during this phase. As it runs on operates in SRAM, its overall size (, including code, data, and stack) , must not exceed the capacity of the system SRAM's capacity. The primary task objective of x-boot is to initialize the DRR DDR SDRAM controller and PHY, perform conduct calibration on DRR the PHY and signals, and once calibrated, make the DRAM is ready for use.
Subsequently, x-boot then loads image the images of TF-A (BL31), OP-TEE (BL32), and U-Boot (BL33) from external a storage device into DRAM. Wake up all other The CPU core and let CPU switch from (core 0) then switches itself from 32-bit mode to 64-bit by triggering a software reset. It proceeds to awaken other cores (core 1, 2, 3) and transitions them to 64-bit mode. Finally, all cores execute TF-A.
| Table of Contents |
|---|
Features
Output log at UART0 (at 115,200 bps set by i-boot).
Support loading firmware of DDR3, DDR4 or LPDDR4 from boot devices.
Support initialize DDR controller and PHY.
Support 1D and 2D training of PHY for DDR3, DDR4, and LPDDR4.
Support loading image of TF-A (BL31), OP-TEE (BL32) and U-Boot (BL33) from boot devices.
Support secure-boot:
Verify digital signature of fip (TF-A and OP-TEE) and U-Boot images.
Decrypt fip image.
Support warm-boot.
Switch CA55 to 64-bit mode and jump to run TF-A.
Support read and write OTP bit using Sunplus OTPTool through UART0.
...