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Files | Descriptions |
platform_def.h | Contains most definitions of platform, include DRAM base address, size, and etc. |
sp_mmap.h | Contains definitions of address DRAM, registers, GIC base and etc.. |
sp_pm.h | Contains definitions of registers watchdog. |
Log of BL31 and explanation
Line 1-2: Banner (version) of BL31.
Line 3-7: BL31 is in the process of initializing itself.
Line 8: BL21 is initializing BL32 (OP-TEE).
Line 9-12: Log of OP-TEE, redirected to UART0.
Line 10: Banner (version) is OP-TEE.
Line 11-12: Indicate that the primary CPU (core 0) has completed initialization in secure mode and then switches back to normal world boot.
Line 13-15: OP-TEE is completed initialization and is preparing to execute U-Boot, located at 0x500040.
| Code Block |
|---|
NOTICE: BL31: v2.4(release):5dd30df
NOTICE: BL31: Built : 02:10:02, Jan 14 2024
NOTICE: BL31: Detected SP7350 SoC (0a30)
INFO: ARM GICv2 driver initialized
INFO: BL31: Platform setup done
INFO: BL31: Initializing runtime services
NOTICE: PSCI: plat_setup_psci_ops
INFO: BL31: Initializing BL32
I/TC:
I/TC: OP-TEE version: 150e2ba (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Sat Jan 13 06:09:33 PM UTC 2024 aarch64
I/TC: Primary CPU initializing
I/TC: Primary CPU switching to normal world boot
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x500040
INFO: SPSR = 0x3c9 |