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During the boot process, the image files of BL31 (TF-A), BL32 (OP-TEE), and BL33 (U-Boot) are loaded by the second-stage boot-loader, x-boot (BL2). Following this, x-boot (BL2) facilitates the transfer of control to BL31 (TF-A). BL31 operates as a secure monitor with Exception Level 3 (EL3) privileges, adhering to the AArch64 architecture standard.
The BL31 image is loaded and functions at the address 0x200000. The device tree source (dts) for the SP7350 platform reserves a one-megabyte area beginning at 0x200000 for BL31. Please refer to the dts node provided below
| Code Block |
|---|
reserved-memory {
:
:
/* TF-A reserve memory: 0x200000-0x2fffff, total 1M */
tfa_reserve@200000 {
reg = <0x0 0x200000 0x0 0x100000>;
no-map;
};
:
:
}; |
BL31
As the final security barrier at EL3, BL31 operates differently from BL1 and BL2, as it is not a one-time execution. As implied by its runtime designation, it continuously provides securely designed services to the non-secure world through SMCs (Secure Monitor Calls). It is responsible for executing BL32.
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Initialization of PSCI services to enable CPU power management operations.
Initialization of the BL32 image for execution in Secure EL1 mode.
Initialization of Non-Secure EL2 or EL1, followed by a jump to execute BL33.
Facilitation of secure and non-secure world transitions.
Distribution of secure service requests.
The device tree source (dts) for the SP7350 platform reserves a one-megabyte area beginning at 0x200000 for BL31. Please refer to the dts node provided below
| Code Block |
|---|
reserved-memory {
:
:
/* TF-A reserve memory: 0x200000-0x2fffff, total 1M */
tfa_reserve@200000 {
reg = <0x0 0x200000 0x0 0x100000>;
no-map;
};
:
:
}; |
Power state coordination interface (PSCI)
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