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Contents
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Software
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Operations
The software components include i-boot, x-boot, TF-A, OP-TEE, U-Boot, Linux, and FreeRTOS. The operation flow of these components is illustrated in the figure below:
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Note that i-boot resides in the chip's internal mask ROM and is a hardware component. x-boot and U-Boot exist temporarily during boot time. Ubuntu server and ROS/ROS2 are optional. After a successful system boot, the stacked software components resemble the figure below:
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CPU (Cortex A55)
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Addressing Space
The CPU of SP7350 supports a 16 GiB addressing space (with 34 address lines), including 8 GiB for DRAM and 4 GiB reserved for CPIO. The addressing space layout is depicted in three figures for 2 GiB DRAM, 4 GiB DRAM, and 8 GiB DRAM.
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In the first 4 GiB address space, the initial 2 GiB is allocated for DRAM, while the remaining 0.25 GiB is reserved for chip internal devices and registers. The second and fourth 4 GiB address spaces are reserved, and the third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus.
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Addressing
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Space for 4 GB DRAM
The first 0.75 GiB address space is allocated for DRAM, followed by 0.25 GiB for chip internal devices and registers. The initial 0.25 GiB of the second 4 GiB address space is allocated for DRAM, while the remaining 3.75 GiB is reserved. The third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus, and the last 4 GiB address space is reserved.
Addressing
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Space for 8 GB DRAM
The first 4 GiB address space is the same as the layout of 4 GiB DRAM. The second 4 GiB address space is allocated for DRAM, and the third 4 GiB address space is for the device (or P-chip) connected with the CPIO bus. The initial 0.25 GiB of the last 4 GiB address space is allocated for DRAM, while the remaining 3.75 GiB is reserved.
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Address
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Map of
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Devices and
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Registers
The detailed address map begins at address 0xf0000000. It includes segments such as 64 MiB of SPI-NOR flash, 64 MiB of SPI-NAND flash, device registers, AO device registers, DDR SRAM controller registers, Cortex-A55 registers, Cortex-M4 registers, CBDMA SRAM, CM4 SRAM, 8-bit NAND flash controller, and ROM.
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