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The picture below is a photo of the C3V-W Dual EVB.
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The following table explains briefly:
Items | Subsystem | Explanations |
1 | Global | 12V DC power input. The diameter of the DC Jack plug is 5.5mm. The power supply current of the adapter must be greater than 1A. |
2 | Global | Main-power switch. Turn down to ON, and turn up to OFF. |
3 | Slave | Pin-headers (3x1, 100mill) of GPIO of Slave C3V-W |
4 | Slave | CM4 console (UA6) of Slave C3V-W. Note GND is at the most bottom pin. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
5 | Slave | Main console (UA0) of Slave C3V-W. Note GND is at the most bottom pin. This is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
6 | Slave | 8 GiB LPDDR4 SDRAM of Slave C3V-W |
7 | Global | Boot configuration switch |
8 | Slave | Jumper header J31. Plug a jumper in to supply power for burning OTP of Slave C3V-W chip. |
9 | Master | Socket of micro SD card of Master C3V-W |
910 | Slave | Type C socket of USB 3.1 Gen1 of Slave C3V-W. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
1011 | Slave | Slave C3V-W chip (15mm x 15mm, 526-pin, TF-BGA) |
1112 | Slave | 8 GiB eMMC of Slave C3V-W |
1213 | Master | RJ-45 socket of Ethernet of Master C3V-W. It supports 10M/100M/1000M speeds. |
1314 | Slave | Socket of micro SD card of Slave C3V-W |
1415 | Master | 8 GiB eMMC of Master C3V-W 15 |
16 | Master | Jumper header J26. Plug a jumper in to supply power for burning OTP of Master C3V-W chip. |
17 | Master | Master C3V-W chip (15mm x 15mm, 526-pin, TF-BGA) |
1618 | Master | Type C socket of USB 3.1 Gen1 of Master C3V-W. It supports Low/Full/High/Super speeds, supports Host, Device and DRD. Current limit of VBUS is 1A. |
1719 | Global | Reset key. Reset CM4 and main power-domains, but does not reset RTC. |
1820 | Master | CM4 console (UA6) of Master C3V-W. Note GND is at the most left pin. It is default serial port of Cortex M4. The default baud rate is 115,200. No parity and 1 stop-bit. |
1921 | Master | 8 GiB LPDDR4 SDRAM of Master C3V-W |
2022 | Master | Main console (UA0) of Master C3V-W. Note GND is at the most right pin. This is default serial port of i-boot, x-boot, Trusted Firmware-A (TF-A), U-Boot and Linux kernel. The default baud rate is 115,200. No parity and 1 stop-bit. |
2123 | Master | Pin-headers (3x1, 100mill) of GPIO of Master C3V-W. |
2.
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Jumpers
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Subsystem
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Descriptions
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Remarks
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J10
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Slave
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Pin-headers (4 pins, 100 mil) for measuring current or voltage.
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J11
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Master
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J12
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Slave
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J13
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Master
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J14
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Slave
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J15
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Master
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J26
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Master
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Plug a jumper in to supply power for burning OTP of Master C3V-W chip.
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No connect by default
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J31
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Slave
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Plug a jumper in to supply power for burning OTP of Slave C3V-W chip.
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No connect by default
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Boot Devices and Configuration
C3V-W Dual EVB supports boot from SD card and eMMC for both Master and Slave C3V-W. Refer to table below of selection of boot configuration switches for Master and Slave C3V-W.
Master | Slave | Boot Configuration Switch |
|---|---|---|
SD Card | SD Card |  |
SD Card | eMMC |  |
eMMC | SD Card |  |
eMMC | EMMC |  |
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3. Map of Addressing Space of Master C3V-W.
Refer to map below for addressing space from view of Master C3V-W when 8 GiB LPDDR4 SDRAM is used:
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Address space starting from 0x2 0000 0000 is mapped to the lowest 4 GiB space of Slave C3V-W via CPIO interface. If CPU of Master C3V-W want to access DRAM of devices of Slave C3V-W, the base address of Slave C3V-W is from 0x2 0000 0000.
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4. Setup CPIO Interface
CPIO interfaces are setup in x-boot for both Master and Slave C3V-W chip. For Master C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Master.
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For Slave C3V-W, please run make xconfig at project top directory. Refer to picture below, when menu pops up, move cursor to “CPIO Mode” and select Slave.
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5. Boot Flow of Software
As normal C3V-W system, Master C3V-W runs i-boot, x-boot, TF-A, OP-TEE, U-Boot, and then Linux while Slave C3V-W stops running after it completes DRAM initialization. Master C3V-W can access any devices including DRAM in Slave C3V-W subsystem.
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6. Log of Master and Slave C3V-W Subsystem
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6.1 Log of Master C3V-W:
| Code Block |
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[ 2.569441] Run /sbin/init as init process /etc/init.d/rcS starts... Mounting other filesystems ... rc.extra [bg] sdcard boot set... [ 2.795789] remoteproc remoteproc0: powering up f800817c.remoteproc [ 2.798426] remoteproc remoteproc0: Booting fw image firmware, size 244280 [ 2.799348] virtio_rpmsg_bus virtio0: rpmsg host is online [ 2.804314] remoteproc0#vdev0buffer: registered virtio0 (type 7) [ 2.810305] remoteproc remoteproc0: remote processor f800817c.remoteproc is now up [ 2.815307] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x0 [ 2.826105] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x1 [ 2.838487] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x2 Boot CM4 firmware by remoteproc extra done End of /etc/init.d/rcS login[143]: root login on 'console' ~ # [ 2.983820] fbcon: Taking over console ~ # devmem 0x2f8800000 0x00000A30 ~ # |
After Linux boots up successfully, you run “devmem 0x2f8800000” to read chip ID of Slave C3V-W. The chip ID of Slave C3V-W should be 0x00000A30. It implies that CPIO is working well.
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6.2 Log of Slave C3V-W:
| Code Block |
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Run draiminit@0xFA20859D bootdevice=0x00000019 Built at Mar 13 2024 19:47:40 dram_init dwc_umctl2_lpddr4_1600_SP7350_for_realchip MT53E2G32D4_C, 2rank, FBGA=D8CJN SDRAM_SPEED_1600 dwc_ddrphy_phyinit_main 20231212 dwc_ddrphy_phyinit_out_lpddr4_train1d2d_3200_SP7350 bootdevice:0x00000019 XBOOT_len=0x0000B278 1D IMEM checksum ok 1D DMEM checksum ok Start to wait for the training firmware to complete v.00 !!! End of CA training. End of initialization. End of read enable training. End of fine write leveling. End of read dq deskew training. End of MPR read delay center optimization. End of Wrtie leveling coarse delay. End of write delay center optimization. End of read delay center optimization. End of max read latency training. Training has run successfully.(firmware complete) bootdevice:0x00000019 2D IMEM checksum ok 2D DMEM checksum ok Start to wait for the training firmware to complete v.00 !!! End of initialization. End of 2D write delay/voltage center optimization. End of 2D write delay/voltage center optimization. End of 2D read delay/voltage center optimization. End of 2D read delay/voltage center optimization. Training has run successfully.(firmware complete) Register programming done!!! Register programming done!!! dram_init_end Done draiminit dram test 0x00800000 - 0x00800400 ---- CPIO-R slave mode Begin ---- VCO: 4.0G, PLL: 1.0G PHY status change: 0x08000001 PHY status check Passed CPIO Initial Finished PHY Mode: 0x0000008D Timer start: 0x00000000 Timer End: 0x000000B2 |
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