...
As normal C3V-W system, Master C3V-W runs i-boot, x-boot, TF-A, OP-TEE, U-Boot, and then Linux while Slave C3V-W stops running after it completes DRAM initialization. Master C3V-W can access any devices including DRAM in Slave C3V-W subsystem.
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7. Log of Master and Slave C3V-W Subsystem
7.1 Log of Master C3V-W:
| Code Block |
|---|
[ 2.569441] Run /sbin/init as init process
/etc/init.d/rcS starts...
Mounting other filesystems ...
rc.extra [bg]
sdcard boot set...
[ 2.795789] remoteproc remoteproc0: powering up f800817c.remoteproc
[ 2.798426] remoteproc remoteproc0: Booting fw image firmware, size 244280
[ 2.799348] virtio_rpmsg_bus virtio0: rpmsg host is online
[ 2.804314] remoteproc0#vdev0buffer: registered virtio0 (type 7)
[ 2.810305] remoteproc remoteproc0: remote processor f800817c.remoteproc is now up
[ 2.815307] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x0
[ 2.826105] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x1
[ 2.838487] virtio_rpmsg_bus virtio0: creating channel rpmsg-tty-raw addr 0x2
Boot CM4 firmware by remoteproc
extra done
End of /etc/init.d/rcS
login[143]: root login on 'console'
~ # [ 2.983820] fbcon: Taking over console
~ # devmem 0x2f8800000
0x00000A30
~ # |
After Linux boots up successfully, you run “devmem 0x2f8800000” to read chip ID of Slave C3V-W. The chip ID of Slave C3V-W should be 0x00000A30. It implies that CPIO is working well.
7.2 Log of Slave C3V-W:
| Code Block |
|---|
Run draiminit@0xFA20859D
bootdevice=0x00000019
Built at Mar 13 2024 19:47:40
dram_init
dwc_umctl2_lpddr4_1600_SP7350_for_realchip
MT53E2G32D4_C, 2rank, FBGA=D8CJN
SDRAM_SPEED_1600
dwc_ddrphy_phyinit_main 20231212
dwc_ddrphy_phyinit_out_lpddr4_train1d2d_3200_SP7350
bootdevice:0x00000019
XBOOT_len=0x0000B278
1D IMEM checksum ok
1D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of CA training.
End of initialization.
End of read enable training.
End of fine write leveling.
End of read dq deskew training.
End of MPR read delay center optimization.
End of Wrtie leveling coarse delay.
End of write delay center optimization.
End of read delay center optimization.
End of max read latency training.
Training has run successfully.(firmware complete)
bootdevice:0x00000019
2D IMEM checksum ok
2D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of initialization.
End of 2D write delay/voltage center optimization.
End of 2D write delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
Training has run successfully.(firmware complete)
Register programming done!!!
Register programming done!!!
dram_init_end
Done draiminit
dram test 0x00800000 - 0x00800400
---- CPIO-R slave mode Begin ----
VCO: 4.0G, PLL: 1.0G
PHY status change: 0x08000001
PHY status check Passed
CPIO Initial Finished
PHY Mode: 0x0000008D
Timer start: 0x00000000
Timer End: 0x000000B2 |
After completing DRAM initialization and training, it sets up and connect CPIO interface and then stop running.