This manual serves as a comprehensive guide for utilizing the C3V-W (LPDDR4) Core Board, a cutting-edge hardware solution tailored for diverse applications. The C3V-W (LPDDR4) Core Board integrates a robust set of components, including the C3V-W chip, an 8 GiB eMMC deviceflash, a 4 GiB LPDDR4 SDRAM, many switching-mode and linear power regulators, and two 120-pin 0.4mm-pitch connectors essential for interfacing with an IO board. Crafted with precision using state-of-the-art 6-layer, HDI PCB technology, this board ensures optimal performance, with LPDDR4 capable of operating at speeds up to 3200 MT/s and eMMC reaching speeds of up to HS200. Customers have the flexibility to design their IO boards tailored to specific applications, leveraging cost-effective 4-layer PCBs. Refer to functional block diagram of C3V-W (LPDDR4) Core Board below:
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All IO pins, except for the eMMC device, are conveniently accessible through the 120-pin fine0.4mm-pitch connectors. Please refer to the pin-assignment diagrams for Connector CN1 and Connector CN2 for detailed pinout information.
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When other power domains are turned off, the AO Power Domain persists, ensuring that CM4 system functionalities are sustained. During this state, the image of the Linux kernel is suspend to (stored in) DRAM, allowing for rapid restoration to normal operation within a few seconds upon user request.
Video Codec Power Domain:
This domain powers the video codec and can be selectively disabled to conserve energy when the video codec is not in use.
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When the CPU is not actively engaged, the CPU Power Domain can be deactivated to conserve power consumption, contributing to overall energy savings. Key voltage specifications for the CPU Power Domain:
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SYS_0V8 = DPHY_0V8 = MIPI_0V8: 0.8V
SYS_1V8: 1.8V
SYS_3V: 3.0V
SYS_3V3: 3.3V
SYS_5V: 5V5.0V