Page Comparison

Disclaimer

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• CPU: Quad ARM Cortex-A55

  • 1.8 GHz (2.1 GHz for specific components)

  • Cache

    • L1 Cache: 32kB I-cache / 32kB D-cache

    • L2 Cache: 128kB

    • L3 Cache: 1MB

  • Support NEON advance SIMD architecture & Floating-point

  • Support DVFS

    • 0.5GHz ~1.5GHz @0.8V 85°C

    • 1.5GHz ~1.8GHz @TT 0.84V 85°C

    • 1.5GHz ~1.8GHz @SS 0.94V 85°C

  • Support individual core power down

  • Support 2/4 core configurable by e-fuse (OTP)

  • Support maximum frequency limited by e-fuse (OTP)

    • Maximum limited to 1.5GHz, 1.8GHz, and 2.1 GHz

  • Support Coresight debug solution

    • JTAG interface

    • CTI and PMU

    • ETB: 1k to 4k bytes buffer size per core

• NPU: AI and Parallel Processing Engine

  • Verisilicon VIP9000DI, with 256kB SRAM

  • Up to 4.5 TOPS (@900MHz) computing power

  • Support configurable operating frequency

  • Support indivudual controllable power domain.

  • Support OpenCL and OpenVX with Neural Network Extension

• MCU: ARM Cortex-M4

  • Support FPU

  • Support 400MHz, 200MHz, 100MHz and 25MHz

  • Support JTAG and SWD interface

• DDR SDRAM

  • LPDDR4-3200, DDR4-3200, DDR3-1866

  • 2 channels, 16 bits per channel

  • Up to 8GB memory capacity

  • Support IO retention

• Internal SRAM

  • 256kB at main power domain

  • 384kB at CM4 (AO) power domain

    • For CM4 operation and DRAM IO retention data

• AXI DMA

  • Support 16 channels

  • Support memory-to-memory copy

  • Support hardware handshake for 8-bit NAND controller

• AHB DMA

  • Support 16 channels

  • Support memory-to-memory copy

  • Support hardware handshake for I2C and SPI controllers

• Boot Devices

  • eMMC devicce

    • Support both 1.8V and 3.3V IOVDD

    • Support SDR up to 200 MHz (only for IOVDD = 1.8V)

    • Support DDR up to 160 MHz (only for IOVDD = 1.8V)

  • SD card

    • Support SD 3.0

    • Support SDR up to 200MHz

  • SPI-NAND flash

    • Support SLC NAND only

    • Support up to 150Mz (only for 1.8V)

    • Support 1 or 2 planes 2k page-size dice

    • Support 1 plane 4k page-size dice

  • 8-bit NAND flash

    • Support 1.8V and 3.3V

    • Support 2k/4k/8 page-size dice

    • Support synchronous mode

  • SPI-NOR flash

    • Support 1/2/4-bit mode

    • Support 1.8V and 3.3V

    • Support up to 100Mz (only for 1.8V)

• In-system Programming for Flash Devices

  • eMMC, SPI-NAND, 8-bit NAND, and SPI-NOR

  • In-system programming through USB flash drives or SD cards

• Security

  • Support AES-128/192/256 encryption and decryption ECB, CBC, CTR mode

  • Support RSA

    • 256/512/1024/2048 bits encryption

    • modular exponentiation

  • Support HASH

    • SHA-2 256/512

    • SHA-3 224/256/384/512

    • MD5

  • GHASH for AES GCM mode

  • Support POLY 1305

  • Support Pseudo RNG

  • Support ARM TZC-400

  • Support secure boot

• SDIO

  • Support SD 3.0

  • Support transfer rate up to 104MB/s (UHS-1)

• Video and image codec

  • H.264/MVC, VP8 and JPEG encoding

  • H.264/SVC and JPEG decoding

  • Individual controllable power domain.

• USB3.1 (Gen. 1) Interface

  • Compliant to USB 3.1 Gen1 with DRD

  • Data rate up to 5Gbps

  • Integrated PHY

  • Support 4 sets of end-points (1 control and 3 data)

• USB2.0 Interface

  • Compliant to USB 2.0

  • Support OTG 1.0

  • Support High and Full speeds

    • 4 in: 3 bulk/interrupt; 1 bulk/interrupt/isochronous

    • 4 out: bulk/interrupt; 1 bulk/interrupt/isochronous

• MIPI CSI RX

  • 1 MIPI-CSI2 RX 4D1C (1.5 Gbps per lane), support 4 virtual channel

  • 1 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel

  • 2 MIPI-CSI2 RX 2D1C (1.5 Gbps per lane), support 2 virtual channel

    • Shared pins with CPIO (when CPIO disable, MIPI CSI RX enable)

    • 2 MIPI-CSI2 RX can be combined as 1 MIPI-CSI2 RX 4D1C, support 4 virtual channel

  • Max resolution: 2688x1944

• MIPI CSI/DSI TX

  • One MIPI TX output for either CSI or DSI

  • 4 lanes with 1.5Gbps per lane

  • DSI TX resolution up to 1920x1080

  • CSI TX resolution up to 3840x2880

• Audio Interfaces

  • One bidirectional I2S

  • Two unidirectional I2S

  • One 16-channel TDM

  • Configurable serial clock frequency

  • Support 16 bit audio format

  • Support both master and slave mode

  • Compliant with the IIS/PCM standard

• Ethernet Controller

  • Support 10/100/1000 Mbps data rate

  • Support RGMII and RMII interface (1.8V)

  • Support IEEE1588

• ADC

  • 12-bit SAR ADC with 4-channel

  • Sampling rate up to 1MHz

• PWM

  • Support 12 bits resolution

  • Support pre-scaling factor from 1 to 512

• Real-Time-Clock (RTC)

  • Independent Always-On power domain

  • 64 bits free-run timer with 32.768 kHz clock input

• SPI/I2C/UART

  • Up to seven UART interfaces

  • Up to six SPI interfaces (5 master, and 1 slave)

  • Up to ten I2C interfaces

• GPIO

  • Support total 106 GPIOs

  • Support software programmable driving strength for all GPIOs

  • Support 60 GPIOs with 1.8V/3.3V capability

    • 3 groups in AO-power domain

    • 2 groups in main-power domain

• Watchdog Timer

  • 32-bit counter

  • Up to 223 second

• Mailbox

  • For inter-processor communication between CA55 and CM4

• RTC

  • 32.768 kHz crystal

• Semaphore

  • Support read lock and write unlock

  • Support 16 channels

• Thermal Sensor

  • Placed at between CPU and NPU

  • Support two threshold temperatures (default disable)

    • Alarm threshold, interrupt to CPU

    • Shutdown threshold, for resetting all system

• Multi-Function Interface (MFI) and CPIO

  • Selectable proprietary CPIO and MIPI CSI-RX interfaces

  • CPIO interface

    • Supports 4 data lanes for both TX and RX, provides 1.0 GiB/s bandwidth

    • Support hardware auto calibration

    • Support hardware auto and/or software programmable SWAP and CROSSOVER modes

    • Support data swap

• Package: 15x15mm² FCCSP

3. Power Domains

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4. CPU, MCU, NPU and DRAM Interface

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4.1 CPU

The CPU consists of a quad-core ARM Cortex-A55 architecture, featuring a floating-point unit (FPU) and NEON™ SIMD processing. Clock rates can reach up to 1.8GHz, with support for dynamic frequency scaling to optimize energy consumption. Cache memory comprises 32KB L1 I-cache, 32KB L1 D-cache, 128KB L2 cache, and 1MB L3 cache. TrustZone™ technology enhances security capabilities.

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4.2 MCU

The MCU core is based on the ARM Cortex-M4 architecture, equipped with a floating-point unit. Operating at clock rates of 25MHz, 100MHz, 200MHz, and 400MHz, the MCU features an independent on-chip power domain. This allows the MCU to remain operational even when other chip power domains are shut off, enabling the implementation of deep-sleep mode. When CPUs return from deep sleep, DRAM must be configured in self-retention mode to maintain the previous state.

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4.3 NPU

The NPU operates at clock rates of up to 900 MHz, delivering computing performance of up to 4.5 TOPS (Trillion Operations Per Second). Optimized for AI models based on convolutional neural networks, it includes a Parallel Processing Unit (PPU) with 32-bit floating-point pipelining and threading. For software development in parallel computing and video computing, both OpenCL and OpenVX are supported. The NPU resides in an independent power domain, allowing individual power-down control.

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4.4 DRAM Interface

The supported types of DRAM include:

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The DRAM interface provides two channels with a 16-bit width for each channel. It supports up to 4GB DRAM chips, with a maximum total capacity of 8GB. To facilitate system suspending, the DRAM includes a self-refresh function for data retention when the chip core is powered down.

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5. Boot Devices and In-System Programming

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5.1 Boot Devices

The C3V-W (CPU) can be booted from various storage devices, including eMMC device, SD card, SPI-NAND, SPI-NOR, or 8-bit NAND flash.

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5.2 In-System Programming (ISP)

System code can be programmed using either a USB flash drive connected to USB2 or USB3, or through an SD card.

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6. USB Interfaces

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6.1 USB 3.1 Gen 1 DRD

The USB3 interface is compliant to USB 3.1 Gen 1 standard with data rate of 5Gbps and supporting Dual-Role Device (DRD). USB 3.0 Dual-Role Data (USB3 DRD) enables a USB device to act as both a host and a peripheral device. This capability is also known as USB On-The-Go (USB OTG) in the context of USB 2.0.

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Note: All output endpoints share a buffer, while each input endpoint has its own input buffer.

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6.2 USB 2.0 OTG

USB 2.0 supports both High-speed and Full-speed transfers and is compatible with both host and device configurations. USB On-The-Go (OTG) extends the capabilities of USB 2.0 by enabling devices to dynamically switch between host and peripheral roles as needed. Note that C3V-W only supports SRP and HNP, and does not supports ADP.

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This breakdown illustrates the available options for configuring USB 2.0 endpoints.

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7. Ethernet Controller

The Ethernet Media Access Controller (MAC) is a crucial component in networking systems, facilitating high-speed data transfer. It supports transfer rates of 10/100/1000 Mbps and interfaces with external transceivers (PHY) to establish Ethernet connectivity.

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7.1 Register Configuration

The GMAC_PHYSEL (0xF88001DC[12]) register and CLKGEN_GMACPHY_SEL[1:0] (0xF88001DC [11:10]) register dictate the interface mode and corresponding TXC clock frequency. Proper configuration of the GMAC_PHYSEL and CLKGEN_GMACPHY_SEL registers is essential for ensuring optimal performance in each operating mode. Here's a breakdown of the configurations:

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7.2 Pin Connections

The following table illustrates the pin connections for both RGMII (GMAC_PHYSEL = 0) and RMII (GMAC_PHYSEL = 1) interfaces. It's important to note that C3V-W only supports 1.8V PHY, regardless of the selected interface type.

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Understanding and correctly implementing these configurations ensure seamless operation and optimal performance of the Ethernet MAC interface.

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8. MIPI Interfaces and Display

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8.1 MIPI CSI RX

The C3V-W boasts six MIPI CSI RX channels, although two are not accessible in this package configuration. The MIPI RX0, RX1, RX2, RX3, and RX4 channels support 2 data lanes (2D1C) each with 2 virtual channels. Additionally, the MIPI RX5 channel accommodates 4 data lanes (4D1C) with 4 virtual channels. It's noteworthy that MIPI RX2 can be adapted to support 4 data lanes (4D1C) with 4 virtual channels if MIPI RX3 remains unused. MIPI RX0 and RX1 are not accessible in this particular package variant.

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It's important to note that RX2 and RX3 share pins with the CPIO interface. Therefore, only one of RX2/RX3 or the CPIO interface can be active at any given time.

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8.2 MIPI CSI/DSI TX

One MIPI TX output port that can be configured as CSI for camera output or DSI for display output. This interface provides 4-lane with data rate of 1.5Gbps per lane.

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8.2.1 MIPI DSI TX

• Support data format: RGB888, RGB666 with 18bit, RGB666 with 24bit, RGB565

• Maximum resolution: 1920x1080

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8.2.2 MIPI CSI TX

• Support data format: YUY2, RGB888, RGB565, YUY2-10

• Maximum resolution: 3840x2880

• Image transfer from DRAM can support QoS

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8.3 Display Engine

Display engine features:

• 4-Layer OSD

• Data format support: RGBA8888, RGB565, YUY2, 256 colors

• Maximum source resolution is 1920x1080

• 1 layer image, DRAM fetch format supports NV12, NV16 and YUV444.

• Support scaling up and down

• Maximum source resolution: 3840x2880

• Mixing Function

• Support 5 path mixing, Blending, Transparent, Opacity, Alpha Adjustment

• Support Gamma, 888 to 666 Dither, 888 to 565 Dither

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9. Image and Video Codec

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9.1 Video and JPEG Decoder

The decoder support real-time H.264/SVC and JPEG decoding.

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• Input format: YCbCr 420, YCbYCr422, YCrCb422, CbYCrY 422 and CrYCbY 422

• Output format: YCbCr420, YCbYCr422, YCrYCb422, CbYCrY422 and CrYCbY 422

• Input image size up to 16.7M pixels with max width of 8176 and max height of 8176. Step size is 16 pixels.

• Output image size up to 4096x4096 with step sizes of 8 pixels horizontally and 2 pixels vertically

• Image up and down scaling

• YCbCr to RGB conversion

• 2x2 ordered spatial dithering

• Alpha channel and alpha blending

• Image cropping and digital zoom for JPEG and video stand-alone mode

• Picture in picture

• Image 90/180/270 degrees rotation and horizontal/vertical flip

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9.2 Video and JPEG Encoder

The encoder provides real-time H.264/MVC, VP8 and JPEG encoding.

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• Color space conversion from YCbCr422 to YCbCr 420

• Maximum input resolution up to 8192x8192

• Image cropping

• Down-scaling

• Rotation by 90 or 270 degree

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10. Audio Interface

The audio interface of our system comprises one bidirectional and two unidirectional I2S interfaces. Each interface supports 2-channel (L/R) operation and can function in either master or slave mode, with configurable clock frequency and LRCK polarity.

Within the chip, the I2S interfaces are situated in the Always-On power domain and are connected to the CM4 sub-system. They possess the capability to issue a wakeup signal to activate either the CM4 or CA55 processor cores.

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10.1 Channel 0

Channel 0 is equipped with a bidirectional I2S interface, featuring the following signal specifications:

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10.2 Channel 1

Channel 1 supports either input or output I2S interface, with the following signal specifications:

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10.3 Channel 2

Channel 2 also supports either input or output I2S interface, with the following signal specifications:

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10.4 Clock for external ADC or DAC

Two clock signals are provided for external audio ADC or DAC devices:

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10.5 TDM

The TDM interface supports 6 channels for both input and output, with the following signal specifications:

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10.6 SPDIF

A single-channel input or output is provided for debug use through the SPDIF interface:

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11. Analog-Digital Converter

The C3V-W is equipped with a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), multiplexed across four channels. With a rapid sampling rate of up to 1MHz, this ADC delivers swift and efficient data acquisition capabilities. Its broad input range, from 0 to 1.8 volts (as powered by SAR12B_AVDD18), ensures seamless compatibility with an extensive array of input signals and diverse applications.

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12. UART, SPI and I2C

The C3V-W offers a versatile array of interfacing functions, allowing users to configure up to 106 I/O ports for various purposes such as UART, SPI, I2C, SDIO, Ethernet PHY, audio, PWM, and more. In this section, we delve into the functionalities of UART, SPI, and I2C, highlighting their capabilities and configurations.

The UART, SPI, and I2C interfaces, with the exception of UADBG, reside within the Always-On power domain. This design ensures that even when the main power domain is inactive, these interfaces remain operational with the CM4 microcontroller.

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12.1 UART

The C3V-W supports up to seven UART ports, boasting a maximum baud rate of 4 Mbps. Ports 1 and 2 feature hardware flow control for enhanced communication reliability. Additionally, the UADBG port is reserved for chip debugging purposes, featuring connectivity to the internal AXI bus through a specialized secure protocol.

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12.2 SPI

C3V-W boasts up to five SPI ports, each designed to facilitate high-speed data transfer between interconnected devices. Among these, SPI 0, 1, 2, 3, and 4 operate as master controllers, while SPI 5 assumes the role of a slave controller. With a clock rate of up to 25MHz, these SPI ports offer rapid data transmission, catering to a diverse range of application requirements.

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12.3 I2C

C3V-W offers up to ten distinct ports, providing ample flexibility for system integration. These ports can function as either masters or slaves, facilitating bidirectional communication between interconnected devices. Moreover, the ports exhibit remarkable versatility, supporting Standard Mode (100 kHz), Fast Mode (400 kHz), and High-Speed Mode (1.2 MHz) for clock (SCL) frequencies.

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13. RTC, STC, PWM and Clock Generators

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13.1 Real-Time Clock

A 64-bit timer operates with a 32.768 kHz clock in an independent RTC power domain. Registers allow configuration of the timer within the range of 0 to 59 seconds, 0 to 59 minutes, 0 to 23 hours, and 0 to 65536 days. A maskable alarm interrupt can be set by configuring the second, minute, hour, and day.

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13.2 System Time Counter (STC)

The C3V-W features seven System Time Counters (STCs), each comprising a 64-bit STC counter, a 24-bit RTC counter, a 32-bit watchdog counter, three 32-bit timers (timer 0, 1, 2), a 64-bit timer (timer 3), and a 34-bit ATC counter.

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13.3 Pulse-Width Modulation (PWM)

Up to four 12-bit PWM channels are available with a pre-scaling factor from 1 to 512. The duty cycle is configurable from 0 to 100%, and the polarity of the output is also configurable.

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13.4 Clock Generators

Various clocks can be generated by a digital PLL and output through GPIO pins, including CLKMCU, CLKWIFI, and CLKGNCMA. CLKRTC and CLKPHY output fixed frequencies of clocks. Note that digital PLL clocks offer average frequency, not stable frequencies. The source clock rate is 800 MHz, and the output clock rate is achieved by dividing the source clock rate by a divisor configured in registers. Clocks from the digital PLL may suffer from high jitter if the frequency of the generated clock is not divisible by the source frequency of the digital PLL.

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14. GPIO

Up to 106 GPIOs are available, with 60 GPIO at 1.8V/3.3V voltage level and others at 1.8V voltage level. Driving strength is programmable.

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14.1 Group of GPIO

The GPIO pins of C3V-W are organized into 10 distinct groups, each with its dedicated power supply. Refer to the table below for a breakdown of the power domains, supplying voltages, hardware pin names, and the corresponding supplying power pins for all IO pins of C3V-W:

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This table delineates the power domains and their respective supplying voltages, along with the hardware pin names and their corresponding supplying power pins for all IO pins of C3V-W. Such organization facilitates efficient management and utilization of GPIO pins within the system.

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14.2 Default State of Power-on of GPIO

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14.2.1 Table of Default State of Power-on of GPIO

• ST (Schmitt Trigger Input): 1 indicates enabled, 0 indicates disabled.

• DS[3:0] (Driving Strength): Refer to Table 15.4.1 for values.

• SL (Slew Rate Control): 1 indicates enabled, 0 indicates disabled.

• PE (Pull Enable): 1 indicates pull-up/down enabled, 0 indicates disabled.

• PS (Pull Selector): 1 indicates pull-up, 0 indicates pull-down.

• SPU (Strong Pull Up): 1 indicates enabled, 0 indicates disabled.

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14.2.2 Table of Default State of Power-on of GPIO

• ST (Schmitt Trigger Input): 1 indicates enabled, 0 indicates disabled.

• DS[3:0] (Driving Strength): Refer to Table 15.4.2 for values.

• PU (Pull Up): 1 indicates pull-up, 0 indicates disabled.

• PD (PUll Down): 1 indicates pull-down, 0 indicates disabled.

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14.3 GPIO Interrupt

The C3V-W provides eight external interrupt inputs from configured GPIO pins. The table below lists the external interrupts 0 to 7 and the corresponding pins each interrupt can be configured with:

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In the table, X1 denotes the 1^st signal output position. X2 denotes the 2^nd signal output position. X3 denotes the 3^rd signal output position. X11 denotes the 11^th signal output position.

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14.4 Alternative Function of GPIO

Many GPIO (General Purpose Input/Output) pins offer alternative functions, providing versatility in their usage. These alternatives may consist of one, two, or more sets of output pins. For instance, I2C0 can be configured to output signals either at AO_MX4 (I2C0_CLK) and AO_MX5 (I2C0_DATA), or at AO_MX18 (I2C0_CLK) and AO_MX19 (I2C0_DATA). Below is a comprehensive table listing the alternatives for all GPIO pins:

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In the table, X1 denotes the 1^st signal output position. X2 denotes the 2^nd signal output position. This table serves as a valuable reference for users, facilitating a clear understanding of the alternative functions associated with each GPIO pin. This understanding enables efficient utilization across a range of configurations.

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15 Recommended Operating Conditions

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15.1 Power Supply

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16 Electric Characteristics

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16.1 Driving-strength Table of GPIO

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16.2 Driving-strength Table of DVIO

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16.3 Resistance of Pull-up and down of GPIO

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16.4 Resistance of Pull-up and down of DVIO

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17. Ball Map

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18. Ball Definition

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19.3. Thermal Information

Note: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In application where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.