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Data and clock differential-pairs: 100Ω ±10%
2.4.8.6 Reference Layout of MIPI-RX2
In the reference layout below, the nets of the MIPI-RX2 are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω for all pairs. From top to bottom, the differential pairs are: (MIPIRX2_DP2, MIPIRX2_DN2), (MIPIRX2_DN0, MIPIRX2_DP0), and (MIPIRX2_DP3, MIPIRX2_DN3).
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From top to bottom, the differential pairs are: (MIPIRX2_CN, MIPIRX2_CP), and (MIPIRX2_DP1, MIPIRX2_DN1).
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2.4.8.7 Reference Layout of MIPI-RX3
In the reference layout below, the nets of the MIPI-RX3 are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100Ω for all pairs. From top to bottom, the differential pairs are: (MIPIRX3_DP0, MIPIRX3_DN0), and (MIPIRX3_CN, MIPIRX3_CP).
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The differential pair is: (MIPIRX3_DN1, MIPIRX3_DP1).
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2.4.8.8 Reference Layout of MIPI-RX4
In the reference layout below, the three differential pairs of MIPI-RX4 are initially routed at Layer 1, and subsequently transition to Layer 6 towards a near the connector. It is crucial to maintain a controlled differential impedance of 100Ω for all pairs. From top to bottom, the differential pairs are: (MIPI4_DP0, MIPI4_DN0), (MIPI4_SP, MIPI4_SN), and (MIPI4_DP1, MIPI4_DN1).
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2.4.8.
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9 Reference Layout of MIPI-RX5
In the reference layout below, the five differential pairs of MIPI-RX5 are initially routed at Layer 3, and subsequently transition to Layer 6 towards a near the connector. It is crucial to maintain a controlled differential impedance of 100Ω for all pairs. From top to bottom, the differential pairs are: (MIPI5_DN2, MIPI5_DP2), (MIPI5_DN0, MIPI5_DP0), (MIPI5_SP, MIPI5_SN), (MIPI5_DN1, MIPI5_DP1), and (MIPI5_DP3, MIPI5_DN3).
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In the reference layout below, the five differential pairs of MIPI-TX are initially routed at Layer 1, and subsequently transition to Layer 6 towards a near the connector. It is crucial to maintain a controlled differential impedance of 100Ω for all pairs. From top to bottom, the differential pairs are: (MIPITX_DP3, MIPITX_DN3), (MIPITX_DP2, MIPITX_DN2), (MIPITX_SP, MIPITX_SN), (MIPITX_DP1, MIPITX_DN1), and (MIPITX_DP0, MIPITX_DN0).
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In the reference layout below, the nets of the RGMII are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 towards a near the connector. Please maintain a controlled impedance of 50Ω for all RGMII signals throughout.
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