Disclaimer
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Channel | Data Lane # | Virtual Channel # | Remarks |
|---|---|---|---|
RX0 | 2 | 2 | Not available in this package |
RX1 | 2 | 2 | Not available in this package |
RX2 | 2 | 2 | |
RX3 | 2 | 2 | Not available for version A chips. |
RX4 | 2 | 2 | |
RX5 | 4 | 4 |
It's important to note that RX2 and RX3 share pins with the CPIO interface. Therefore, only one of RX2/RX3 or the CPIO interface can be active at any given time.
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Symbol | Parameters | Min. | Typ. | Max. | Unit |
t1 | RMII clock period |
| 20 |
| nS |
| RMII clock duty cycle | 35 |
| 65 | % |
t2 | TX_Data, TX_EN setup to RMII clock rising | 4 |
|
| nS |
t3 | TX_Data, TX_EN hold from RMII clock rising | 2 |
|
| nS |
t4 | RXD, CRSDV setup time | 2 |
|
| nS |
t5 | RXD, CRSDV hold time | 2 |
|
| nS |
16.6 Power Consumption
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Symbol
...
Parameters
...
Conditions
...
Min.
...
Typ.
...
Max.
...
Unit
...
I08
...
0.8V supply current
...
Chip leakage is 182 mA @0.8V
including:
CA55 @1.8GHz,
NPU @900MHz with 0.85V
...
2675
...
4243
...
mA
...
I1.1
...
1.1V supply current
...
280
...
285
...
mA
...
I1.8
...
1.8V supply current
...
42.5
...
44.7
...
mA
...
I3.0
...
3.0V supply current
...
65.5
...
67
...
mA
...
I3.3
...
3.3V supply current
...
199.5
...
213.5
...
mA
...
Power Dissipation
...
3.38
...
4.69
...
W
Note: The power consumption is based on a chip with leakage current equals to 182 mA.
Note: The NPU and CA55 power is based on 0.85V.
Note: The test condition is defined by Vendor.
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Powers | Nominal Voltage (V) | FF corner (average) | Sim (peak) | Unit | |
37°C | 120°C | 85°C | |||
DPHY_0V8 | 0.8 | 320 | 430 | 420 | mA |
MIPI_0V8 | 0.8 | 68 | 90 | mA | |
SYS_0V8 | 0.8 | 363 | 550 | 2140 | mA |
VDD_CA55 | 0.85 | 895 | 1889 | 940 | mA |
VDD_NPU | 0.85 | 930 | 1078 | 5390 | mA |
VDD_VV | 0.8 | 262 | 397 | 1670 | mA |
VDDQ | 1.1 | 337 | 344 | mA | |
MIPI_1V8 | 1.8 | 6.5 | 6.7 | 19 | mA |
SYS_1V8 | 1.8 | 20 | 21 | mA | |
SYS_3V | 3.0 | 75 | 76 | mA | |
SYS_3V3 | 3.3 | 210 | 237 | mA | |
AO_0V8 | 0.8 | 45 | 80 | mA | |
AO_1.8V | 1.8 | 19 | 20 | mA | |
AO_3.0V | 3.0 | 10 | 10 | mA | |
Test conditions (worst case):
A chip with a CA55 (+L3) leakage current of 182 mA at 25°C.
CA55 runs at 1.8GHz, 0.85V, 70% duty
NPU runs at 900MHz, 0.85V, 50% duty
17. Ball Map
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18. Ball Definition
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