This manual serves as a guide for utilizing the C3V-W Dual (LPDDR4) EVB. The C3V-W Dual (LPDDR4) EVB comprises two subsystems: one is Master C3V-W subsystem, which operates Linux software, and the other is Slave C3V-W subsystem, offering additional 3.75 GiB DRAM, a NPU, and various peripherals (including USB3, SD card, GPIO, and more). Please refer to the functional block diagram of the C3V-W Dual (LPDDR4) EVB. The Master C3V-W subsystem features 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, an SD card slot, USB3 Type C port, and a 10M/100M/1000M Ethernet port. On the other hand, the Slave C3V-W subsystem includes 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, an SD card slot, and USB3 Type C port. The CPIO is engineered with three primary objectives:
With mounting two NPUs, NN computing power is doubled.
With mounting another 3.75GB DRAM on slave C3V-W, comprise 11.75GB DRAM totally, for LLM testing.
Test the CPIO functionality.
The original design purpose of CPIO is to allow C3V-W to connect to a P-chip (peripheral chip) through CPIO bridge. The P-chip is a custom-designed peripheral. C3V-W, the C-chip (computing chip), can connect to either a P-chip, or another C-chip.
The C3V-W Dual (LPDDR4) EVB comprises two subsystems: one is Master C3V-W subsystem, which operates Linux software, and the other is Slave C3V-W subsystem, offering additional 3.75 GiB DRAM, a NPU, and various peripherals (including USB3, SD card, GPIO, and more). Please refer to the functional block diagram of the C3V-W Dual (LPDDR4) EVB. The Master C3V-W subsystem features 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, an SD card slot, USB3 Type C port, and a 10M/100M/1000M Ethernet port. On the other hand, the Slave C3V-W subsystem includes 8 GiB eMMC, 8 GiB LPDDR4 SDRAM, an SD card slot, and USB3 Type C port. The CPIO bus connects both subsystems together.
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3. Map of Addressing Space of Master C3V-W.
Refer to the map below for addressing the address space from view the perspective of Master C3V-W when using 8 GiB LPDDR4 SDRAM is used:
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Lower 3.75 GiB
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Space: This is mapped to the bottom 3.75 GiB of the 8 GiB DRAM
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in the Master C3V-W subsystem.
Device Registers (0.25 GiB): A contiguous 0.25 GiB space is allocated for device registers specific to the Master C3V-W subsystem.
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Upper 4 GiB
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Space: This is mapped to the upper 4 GiB of the 8 GiB DRAM
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in the Master C3V-W subsystem.
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Slave C3V-W Subsystem (4 GiB): Starting from address 0x2 0000 0000, a segment of 4 GiB is dedicated to the Slave C3V-W subsystem.
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Remaining Lower DRAM Space (0.25 GiB): The final 0.25 GiB space, commencing from address 0x3 0000 0000, is allocated for the remaining portion of the lower 4 GiB of the 8 GiB DRAM
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in the Master C3V-W subsystem.
In this configuration, the address space beginning from 0x2 0000 0000 is specifically assigned to the lowest 4 GiB space of the Slave C3V-W subsystem through the CPIO interface. Consequently, if the CPU of the Master C3V-W board intends to access the DRAM of devices on the Slave C3V-W subsystem, it must reference the base address of the CPIO interface. Consequently, if the CPU of the Master C3V-W board intends to access the DRAM of devices on the Slave C3V-W subsystem, it must reference the base address of the Slave C3V-W subsystem, starting from 0x2 0000 0000.
The memory node in device-tree source should looks like this:
| Code Block |
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memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0xf0000000>, /* Lower 3.75 GiB */
<0x1 0x0 0x1 0x00000000>, /* Upper 4 GiB */
<0x2 0x0 0x0 0xf0000000>, /* Slave C3V-W Subsystem 4 GiB */
<0x3 0x0 0x0 0x10000000>; /* Remaining Lower DRAM 0.25 GiB */
}; |
This configuration ensures that the Master C3V-W can efficiently access both its own memory and the memory allocated to the Slave C3V-W subsystem, starting from 0x2 0000 0000.
4. Setup the CPIO Interface
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