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In the reference layout below, the nets of the RGMII are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 near the connector. Please maintain a controlled impedance of 50Ω for all RGMII signals throughout.
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2.4.10 Ethernet Interface (RMII)
2.4.10.1 General Rules
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs in routing, as these can introduce impedance mismatches and signal reflections.
2.4.10.2 Trace Impedance
TXD[1:0], TXEN, REF_CLK, RXD[1:0] and CRS_DV signals : 50Ω ±10%