9.1. Power On Sequence
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Figure 9-1 Power On Sequence
Parameter | Symbol | Min | Typ. | Max. | Units |
XTAL clock output stable time | TXTAL | 5 | - | - | us |
AO33V power on timing range | TAO33VPON | 0 | - | 5 | ms |
VDD33 power on timing range | TVDD33PON | 0 | - | 5 | ms |
Operation mode configure time after AO33V and VDD33 power ready (include internal core power ramp up time and reset circuit time cost) | TMODE | 15 | - | - | ms |
9.2. Power
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Down Sequence
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Figure 9-2 Power Off Down Sequence
9.3. Reset State
There are 3 physically event to trigger chip reset.
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