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Quad-core ARM® Cortex-A7(CA7) MPCore operating speed upto 960MHz
NEON multimedia processing engine with SIMDv2/VFPv4 ISA support
32KB L1 I-cache and 32KB L1 D-cache
512KB unified L2 cache
Generic Interrupt Controller (GIC) v2.0
ARM926
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real-time core
Run as real time process unit
ARM926EJS operating speed up to 202 MHz
32KB 16KB L1 I-cache and 32KB 16KB L1 D-cache
8051
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Act as an IO processor for standby mode
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8051 operating speed is 32KHz or 202MHz
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low-power core
Selectable 32KHz or 202MHz operating speed;
Intended to be used as a supervisory core;
Low-power operation—500uA @ 32KHz for the entire IC
All IO and peripherals are accessible by Cortex-A7/ARM926/8051
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One MIPI CSI-RX port
Compliant with the MIPI CSI-2 Specification, rev 1.01 and MIPI D-PHY interface Specification, version 1.1
HS (high speed), LP (low power) modes supported
10Mbps per lane in LP mode
1.0Gbps per lane in HS mode
Support Power-down mode
Support MIPI CSI-2 short and long packet formats
Support MIPI CSI-2 1 4 data lane
Total bandwidth: 810 Mbps4 Gbps
Support MIPI CSI-2 data format: RAW8, RAW10, YUY2
Image Interface to core processor: Support 8 or 10 bits
Color depth / Bits per pixel: Support 8 or 10 bits per pixels
Support CCI or I2C master for Camera Control Interface
Camera pixel resolution: 1328x864 1920x1080 (Including non-image data)
Jira Legacy showSummary false server System JIRA serverId 0f231b3b-db0a-3c3b-bca2-14b07836a5c1 key FAQ-4
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