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10.8.1 Registers Memory Map
Address | Group No. | Register Name | Description |
|---|---|---|---|
0x9C002880 | G81.0 | icm0_cfg0 | ICM0 Config Register 0 |
0x9C002884 | G81.1 | icm0_cfg1 | ICM0 Config Register 1 |
0x9C002888 | G81.2 | icm0_cfg2 | ICM0 Internal Counter Scaler |
0x9C00288C | G81.3 | icm0_cfg3 | ICM0 Test Signal Scaler |
0x9C002890 | G81.4 | icm0_cnt | ICM0 Interrupt Trigger Counter Value |
0x9C002894 | G81.5 | icm0_pulse_width_h | ICM0 Pulse Width H |
0x9C002898 | G81.6 | icm0_pulse_width_l | ICM0 Pulse Width L |
0x9C00289C | G81.7 | icm1_cfg0 | ICM1 Config Register 0 |
0x9C0028A0 | G81.8 | icm1_cfg1 | ICM1 Config Register 1 |
0x9C0028A4 | G81.9 | icm1_cfg2 | ICM1 Internal Counter Scaler |
0x9C0028A8 | G81.10 | icm1_cfg3 | ICM1 Test Signal Scaler |
0x9C0028AC | G81.11 | icm1_cnt | ICM1 Interrupt Trigger Counter Value |
0x9C0028B0 | G81.12 | icm1_pulse_witdh_h | ICM1 Pulse Width H |
0x9C0028B4 | G81.13 | icm1_pulse_width_l | ICM1 Pulse Width L |
0x9C0028B8 | G81.14 | icm2_cfg0 | ICM2 Config Register 0 |
0x9C0028BC | G81.15 | icm2_cfg1 | ICM2 Config Register 1 |
0x9C0028C0 | G81.16 | icm2_cfg2 | ICM2 Internal Counter Scaler |
0x9C0028C4 | G81.17 | icm2_cfg3 | ICM2 Test Signal Scaler |
0x9C0028C8 | G81.18 | icm2_cnt | ICM2 Interrupt Trigger Counter Value |
0x9C0028CC | G81.19 | icm2_pulse_witdh_h | ICM2 Pulse Width H |
0x9C0028D0 | G81.20 | icm2_pulse_width_l | ICM2 Pulse Width L |
0x9C0028D4 | G81.21 | icm3_cfg0 | ICM3 Config Register 0 |
0x9C0028D8 | G81.22 | icm3_cfg1 | ICM3 Config Register 1 |
0x9C0028DC | G81.23 | icm3_cfg2 | ICM3 Internal Counter Scaler |
0x9C0028E0 | G81.24 | icm3_cfg3 | ICM3 Test Signal Scaler |
0x9C0028E4 | G81.25 | icm3_cnt | ICM3 Interrupt Trigger Counter Value |
0x9C0028E8 | G81.26 | icm3_pulse_witdh_h | ICM3 Pulse Width H |
0x9C0028EC | G81.27 | icm3_pulse_width_l | ICM3 Pulse Width L |
0x9C0028F0 | G81.28 | reserved | reserved |
0x9C0028F4 | G81.29 | reserved | reserved |
0x9C0028F8 | G81.30 | reserved | reserved |
0x9C0028FC | G81.31 | reserved | reserved |
10.8.2 Registers Description
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm0 clk sel | 8:6 | RW | ICM0 Clock Source Select (Default value 是哪一個 ? 麻煩在後方註明 (Default)) |
| icm0 mux sel | 5:3 | RW | Select input signal source. |
| icm0 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | ReservedRESERVED |
| icm0 en | 0 | RW | ICM0 enable When set this bit to 0, it mean disabled input capture module 0 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm0 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm0 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm0 fifo clr | 13 | W1C | Input Capture Module 0 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm0 fifo data drop | 12 | RO | Input Capture Module 0 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | ReservedRESERVED |
| icm0 df times | 8:6 | RW | Input Capture Module 0 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm0 df times+1 times, 0x7: 16 times |
| icm0 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm0 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask BitsExample : If Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm1 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm1 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm1 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm1 en | 0 | RW | ICM1 enable When set this bit to 0, it mean disabled input capture module 1 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm1 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm1 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm1 fifo clr | 13 | W1C | Input Capture Module 1 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm1 fifo data drop | 12 | RO | Input Capture Module 1 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | Reserved |
| icm1 df times | 8:6 | RW | Input Capture Module 1 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm1 df times+1 times, 0x7: 16 times |
| icm10 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm1 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm2 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm2 mux sel | 5:3 | RW | Selec input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm2 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm2 en | 0 | RW | ICM2 enable When set this bit to 0, it mean disabled input capture module 2 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm2 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm2 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm2 fifo clr | 13 | W1C | Input Capture Module 2 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm2 fifo data drop | 12 | RO | Input Capture Module 2 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | Reserved |
| icm2 df times | 8:6 | RW | Input Capture Module 2 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm2 df times+1 times, 0x7: 16 times |
| icm2 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm2 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm3 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm3 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm3 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm3 en | 0 | RW | ICM3 enable When set this bit to 0, it mean disabled input capture module 3 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set this register to 0x00010001 (bit 16 is bit 1 write mask bit).bit16 to 1 (0x 0001) to enable bit0 functionality |
| icm3 fifo full | 15 | RO | Indicate the fifo is full (fifo depth is 7). 0: Non-full 1: Full |
| icm3 fifo empty | 14 | RO | Indicate the fifo is empty (fifo depth is 7). 0: Non-Empty 1: Empty |
| icm3 fifo clr | 13 | W1C | Input Capture Module 3 FIFO Clear 0: Writing 0 to this bit has no effect 1: Clear fifo and icm fifo data drop. Write 1 to clear fifo and icm fifo data drop flag, HW will recover this bit to 0 automatically. |
| icm3 fifo data drop | 12 | RO | Input Capture Module 3 Data Dropped 0: Non-dropped 1: Indicate the fifo data dropped. |
| Reserve | 11:9 | RO | ReservedRESERVED |
| icm3 df times | 8:6 | RW | Input Capture Module 3 Input Signal Debounce Filter Set the debounce times (0-7) of the input signal debounce filter. 0x0-6: icm3 df times+1 times, 0x7: 16 times |
| icm3 ee times | 5:2 | RW | Input capture module interrupt trigger threshold Set 0-15. If set 7, interrupt will be triggered after 8 times edge event. |
| icm3 ee mode | 1:0 | RW | Input capture detect mode Select Others don't care. |
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Field Name | Bit | Access | Description |
Reserved | 31:0 | RO | RESERVED |
81.29 (Reserved)Anchor _GoBack _GoBack
Address: 0x9C0028F4
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserved | 31:0 | RO | RESERVED |
81.30 (Reserved)
Address:0x9C0028F8
Reset: 0x0000 0000
Field Name | Bit | Access | Description |
Reserved | 31:0 | RO | ReservedRESERVED |
81.31 IP Version (ip version)
Address: 0x9C0028FC
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