...
118.31 Debug signals for dma mode (dmadebugReserved)
Address: 0x9C003B7C
Reset: 0x0
這個 debug register 需要嗎 ?
Field Name | Bit | Access | Description | ||
| Reserved | 31:25 | RO | RESERVED | ||
| DMA SMReserved | 24:22 | RO | AXI bus state machine 0x0: Idle state(default) 0x1: Write command and address state 0x2: Read command and address state 0x3: Write Data state 0x4: Read Data state | outcntRESERVED | |
| Reserved | 21:11 | RO | data out counter Account how many byte data has been transfer out to SDRAM or device | incnt | RESERVED |
| Reserved | 10:0 | RO | data in counter Account how many byte data has been transfer into device or SDRAMRESERVED |
RGST Table Group 119 CARD CTL: SD controller
119.0 EMMC Boot Operation Control (boot ctrl)
...