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UART（Universal Asynchronous Receiver Transmitter），是通用异步接收器和发送器的简称。用于串行输入和串行输出设备间通信。串行传输以速度为代价，换取了成本和连线复杂程度的降低。UART提供串行异步接收数据的同步化，发送器和接收器两个部分的并行到串行和串行到并行的数据转换，对于需要将串行数据流转换为并行数据的数字系统，这些功能是必不可少的。串行数据流的同步化是通过给发送数据增加起始位和停止位，以形成一个数据字符而实现的，数据完整性是通过在数据字符中附加一个奇偶位来实现的，由接收器来检验此奇偶位以检验有无任何传输位错误它主要由数据总线接口、控制逻辑、波特率发生器、发送部分和接收部分等组成。
1.1串口协议
通信协议是对数据传送方式的规定，包括数据格式定义和数据位定义等。通信双方必须遵循统一的通信协议。以下是异步串行通信协议规定的字符数据的传送格式。在异步通信中，数据是一帧一帧（包括一个字符代码或一个字节数据）传送的，每一帧的数据格式如下图所示
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在帧格式中，一个字符由四个部分组成：起始位、数据位、奇偶校验位和停止位。
(1)、起始位
起始位（低电位“0”）只占用一位，通知接收设备一个待接收的字符开始到达。通信线上没有数据被传送时处于逻辑1状态。当发送设备要发送一个字符数据时，首先加入一个逻辑0的信号，这个逻辑低电平就是起始位，接收端不断地检测线路的状态，接收设备检测到这个逻辑低电平后，就开始准备接受数据位信号。字符的起始位还被用作同步接收端的时钟，以保证以后的接收能正确进行。起始位能使设备同步，通信双方必须在传送数据位前协调同步。
(2)、数据位
起始位后面紧接着是数据位，它可以是5位、6位、7位或8位。当接收设备接收到起始位后，紧接着就会收到数据位。这些数据位被接收到移位寄存器中，构成传送数据字符。在字符数据传送过程中，数据位从最低有效位开始发送，依次顺序在接收设备中被转换为数据。
(3)、奇偶校验位
数据位发送完，可发送奇偶校验位。奇偶校验位只占一位，也可以不用校验位，则这一位就可省略，或也可用这一位来确定这一帧中的字符所代表信息的性质（地址/数据等）。奇偶校验属于有限差错检测，通信双方需约定一致的奇偶校验方式。如果选择偶校验，那么组成数据位和奇偶位的逻辑1的个数必须是偶数；如果选择奇校验，那么逻辑1的个数必须是奇数。
(4)、停止位约定
在奇偶位或数据位（当无奇偶检验时）之后发送停止位。停止位是一个字符数据的结束标志，可以是1位、1.5位或2位的高电平。接收端收到停止位后，表明上一字符已传送完毕，同时，也为接收下一个字符做好准备，如果再接收到0，就是新的字符开始传送。若停止位以后不是紧接着一个字符，则使线路电平保持为高电平（“1”），即空闲位。接收设备收到停止位之后，通信线路上便又恢复逻辑1状态，直至下一个字符数据的起始位到来。
(5)、波特率设置
通信线上传送的所有位信号都保持一致的信号持续时间，每一位的信号持续时间都由数据传送速度决定，即以每秒多少个二进制位来衡量的，这个速度就叫波特率。如果数据以300个二进制位每秒在通信线上传送，那么传送速度为300波特，通常记为300b/s。
(6)、握手信号约定
计算机与modem进行数据交换时，往往通过一些信号线作为交换数据的先提条件，当满足条件时允许数据进行传送；当不满足条件时，处于等待状态，等到允许数据传送的信号发生时，才又开始传送数据。
1.2串并转换
串行通信是将计算机内部要传输的并行数据转换成串行数据，将其通过一根通信线传送；并将接收的串行数据再转换成并行数据送到计算机中。
在计算机串行发送数据之前，计算机内部的并行数据被送到移位寄存器并一位一位地移出，将并行数据转换成串行数据。如下图所示
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在接收数据时，来自通信线路的串行数据被送入移位寄存器，移位保存满8位后并行送到计算机内部
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1.3数据采样
在接收器接收数据时，UART的内部时钟频率往往高于外部数据输入频率。当接收器开始接收信号时，如果内部时钟工作的频率接近或者小于外部数据传输频率，那么在接收器接收数据时，在数据采样的边缘很可能采集不到数据，或者采集到错误的数据。采样的频率可以设置为外部数据传输频率的8倍，16倍。该UART采用的16倍外部时钟频率，采样的波形图如下所示：
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本实例通过对UART总线协议的研究，设计了UART Controller IP, 以此来熟悉UART IP核的设计和验证
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Design Brief
UART (Universal Asynchronous Receiver Transmitter) is short for Universal Asynchronous Receiver and Transmitter. Used for communication between serial input and serial output devices. Serial transmission comes at the cost of speed, in exchange for a reduction in cost and complexity of wiring. UART provides synchronization of serial asynchronous received data, parallel-to-serial and serial-to-parallel data conversion of the transmitter and receiver, for digital systems that need to convert serial data streams to parallel data, these functions Is essential. Synchronization of the serial data stream is achieved by adding start and stop bits to the transmitted data to form a data character. Data integrity is achieved by appending a parity bit to the data character, which is provided by the receiver Check this parity bit to check whether there is any transmission bit error. It is mainly composed of data bus interface, control logic, baud rate generator, sending part and receiving part.
1.1 Protocol
The communication protocol is the regulation of the data transmission method, including the definition of the data format and the definition of the data bits. Both parties must follow a unified communication protocol. The following is the transmission format of character data specified by the asynchronous serial communication protocol. In asynchronous communication, data is transmitted frame by frame (including a character code or a byte of data), and the data format of each frame is shown in the following figure
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In the frame format, a character is composed of four parts: start bit, data bit, parity bit, and stop bit.
(1)、Start bit
The start bit (low level "0") occupies only one bit and informs the receiving device that a character to be received starts to arrive. Logic 1 state when no data is being transmitted on the communication line. When the sending device wants to send a character data, first add a logic 0 signal, this logic low level is the start bit, the receiving end continuously detects the state of the line, the receiving device detects this logic low level and starts Ready to accept data bit signals. The start bit of the character is also used to synchronize the clock of the receiving end to ensure that the subsequent reception can be performed correctly. The start bit enables the device to synchronize, and both parties must coordinate the synchronization before transmitting the data bit.
(2)、Data bit
The start bit is immediately followed by the data bit, which can be 5, 6, 7, or 8 bits. When the receiving device receives the start bit, it immediately receives the data bit. These data bits are received into the shift register and constitute the transmitted data characters. In the transmission of character data, the data bits are sent from the least significant bit and are sequentially converted into data in the receiving device.
(3)、Parity bit
After the data bits are sent, parity bits can be sent. The parity bit only occupies one bit, and the parity bit can be omitted, or this bit can be omitted, or this bit can also be used to determine the nature of the information represented by the characters in this frame (address / data, etc.) Parity check belongs to limited error detection, and both parties in communication must agree on a consistent parity check method. If you select even parity, the number of logic 1s that make up the data bits and parity bits must be even; if you select odd parity, then the number of logic 1s must be odd.
(4)、Stop bit convention
The stop bit is sent after the parity bit or data bit (when there is no parity check). The stop bit is the end mark of a character data, which can be a high level of 1, 5, or 2 bits. After receiving the stop bit, the receiving end indicates that the previous character has been transmitted, and at the same time, it is also ready to receive the next character. If it receives 0 again, the new character begins to transmit. If the stop bit is not followed by a character, the line level is kept high ("1"), which is the idle bit. After the receiving device receives the stop bit, the logic 1 state is restored on the communication line until the start bit of the next character data arrives.
(5)、Baud rate setting
All bit signals transmitted on the communication line maintain a consistent signal duration, and the signal duration of each bit is determined by the data transmission speed, that is, measured by how many binary bits per second, this speed is called the baud rate. If the data is transmitted on the communication line with 300 binary bits per second, the transmission speed is 300 baud, which is usually recorded as 300 b/s.
(6)、Handshake signal agreement
When the computer and modem exchange data, they often use some signal lines as a prerequisite for exchanging data. When the conditions are met, the data is allowed to be transmitted; when the conditions are not met, they are in a waiting state and wait until the signal that allows data transmission occurs. Data transmission begins again.
1.2 Serial-to-parallel conversion
Serial communication is to convert the parallel data to be transmitted inside the computer into serial data and transmit it through a communication line; then convert the received serial data into parallel data and send it to the computer. Before the computer serially sends data, the parallel data inside the computer is sent to the shift register and shifted out bit by bit, converting the parallel data into serial data. As shown below
When receiving data, the serial data from the communication line is sent to the shift register, and after being shifted and saved to 8 bits, it is sent to the computer in parallel
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1.3 Data sampling
When the receiver receives data, the internal clock frequency of the UART is often higher than the external data input frequency. When the receiver starts to receive the signal, if the frequency of the internal clock is close to or less than the external data transmission frequency, when the receiver receives data, it is likely that the data will not be collected at the edge of data sampling, or the wrong data will be collected. The sampling frequency can be set to 8 times, 16 times the external data transmission frequency. The UART uses 16 times the external clock frequency, and the sampled waveforms are as follows:
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In this example, through the research of the UART bus protocol, the UART Controller IP is designed to familiarize with the design and verification of the UART IP core
2 Design specifications
l Support AMBA APB2.0 BUS interface.
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l Support the SW write clear the interrupt.
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3 I/O Ports Description
3.1 APB Register Bus Interface
Name | Direction | Width | Description |
PSEL | Input | 1 | APB Bus Selected Active high to select CTRL group registers. |
PWRITE | Input | 1 | APB Bus Write Enable Active high to enable register bus write operation. Active low to enable register bus read operation. |
PENABLE | Input | 1 | APB Bus Enable Active high to select CTRL group registers. |
PWDATA | Input | 32 | APB Write Data Bus 32 bit data with [31] is most significant bit. |
PADDR | Input | 5 | APB Bus Address 5 bit address bus with [4] is most significant bit. |
PRDATA | Output | 32 | APB Read Data Bus Register read data bus, [31] is most significant bit. Valid when SL_APB_ACK is active. |
3.2 Interrupt Line
Name | Direction | Width | Description |
INT_B | Output | 1 | Interrupt Low active. When finished a operation, INT_B will be active, such as received a packet or error case happened. |
3.3 System Clock and Reset
Name | Direction | Width | Description |
SYSCLK | Input | 1 | System Clock Free running clock, all registers must be synchronous with SYSCLK. |
RST_B | Input | 1 | System Reset Low active. When this pin is asserted, all flip-flops must be reset to their default value. |
3.4 UART interface
Name | Direction | Width | Description |
RX | Input | 1 | Serial Data input |
TX | output | 1 | Serial Data output |
4 Registers File
4.1 Registers List
Address | Name | Access | Description |
5’h00 | LCR | RW | Line Control Register |
5’h01 | SER | RW | Software Enable Register |
5’h02 | BAUD_CNT | RW | Baud-rate Configuration Register |
5’h03 | LSR | RW | Line State Register |
5’h04 | RX_FIFO | RO | RX FIFO Register |
5’h05 | TX_FIFO | RW | TX FIFO Register |
4.2 Line Configuration Register (LCR, Addr = 5’h0)
Default value: 0x0000_0000
Register Bits | Name | Function Description |
1:0 | WORD_SEL | Word Length Select of the UART 00 : 8 bit data transmit and receive 01 : 7 bit data transmit and receive 10 : 6 bit data transmit and receive 11 : 5 bit data transmit and receive |
3:2 | STOP_SEL | Stop Bit Length of the UART 00 : 1 cycle stop bit 01 : 1.5 cycle stop bit 10 : 2 cycle stop bit Default : 1 cycle stop bit |
5:4 | PTY_SEL | Parity Select of the UART 00 : even parity 01 : odd parity 10 : no parity Default : even parity |
31:6 | RSV | Reserved |
4.3 Software Enable Register (SER, Addr = 5’h1)
Default Value: 0x0000_003f
Register Bits | Name | Function Description |
0 | RX_DONE_EN | Data Ready Interrupt Enable Low active, when this bit is 1, Data Ready will not assert interrupt. |
1 | TX_DONE_EN | Transmitted Complete Interrupt Enable Low active, when this bit is 1, Transmitted Complete will not assert interrupt. |
2 | PTY_ERR_EN | Parity Error Interrupt Enable Low active, when this bit is 1, Parity Error will not assert interrupt. |
3 | STOP_ERR_EN | Stop Bit Error Interrupt Enable Low active, when this bit is 1, Stop Bit Error will not assert interrupt. |
4 | RX_FULL_EN | RX FIFO Full interrupt Enable Low active, when this bit is 1, TRX FIFO full will not assert interrupt. |
5 | TX_EMPTY_EN | TX FIFO Empty interrupt Enable Low active, when this bit is 1, TX FIFO empty will not assert interrupt. |
6 | SW_RST | Soft Reset UART High active , the UART will reset when Master writing 1 to this bit |
7 | RX_EN | Receiver FSM Stop Low active , the Receiver will not work when this bit is 1 |
8 | TX_EN | Transmitter FSM Stop Low active , the Transmitter will not work when this bit is 1 |
31:9 | RSV | Reserved |
4.4 Baud-rate Configuration Register (BAUD_CNT, Addr = 5’h2)
Default Value: 0x0000_0000
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Register Bits
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Name
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Function Description
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31:0
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BAUD_CNT
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Baud Rate configure data
Store the count value of baud rate generation
4.5 Line State Register (LSR, Addr = 5’h3)
Default value: 0x0000_0000
Register Bits | Name | Function Description |
0 | RX_DONE | Data Ready High active, the flag of the interrupt that Received a complete packet |
31:9 | RSV | Reserved |
4.4 Baud-rate Configuration Register (BAUD_CNT, Addr = 5’h2)
Default Value: 0x0000_0000
Register Bits | Name | Function Description |
31:0 | BAUD_CNT | Baud Rate configure data Store the count value of baud rate generation |
4.5 Line State Register (LSR, Addr = 5’h3)
Default value: 0x0000_0000
Register Bits | Name | Function Description | |||
0 | RX_DONE | Data Ready High active, the flag of the interrupt that Received a complete packet. The interrupt will be cleaned when this bit is written 0 by master. | |||
1 | TX_DONE | Transmitted Data Complete High active, the flag of the interrupt that Transmitted a complete packet. The interrupt will be cleaned when this bit is written 0 by master. | |||
2 | PTY_ERR | Parity Error High active. The interrupt flag that Parity error. The interrupt will be cleaned when this bit is written 0 by master. | |||
3 | STOP_ERR | Stop Bit Error High active. The interrupt flag that Stop bit error. The interrupt will be cleaned when this bit is written 0 by master. | |||
4 | RX_FULL | RX FIFO Full High active. The interrupt flag that RX FIFO full. The interrupt will be cleaned when this bit is written 0 by mastermaster reads out a data once. | |||
15 | TXRX_DONETransmitted Data CompleteEMPTY | RX FIFO Empty High active, the . The flag of the interrupt that Transmitted a complete packet. The interrupt will be cleaned when this bit is written 0 by master. | 2 | PTY_ERR | Parity Errorthat the RX FIFO empty |
6 | TX_FULL | TX FIFO Full High active. The flag that the TX FIFO full | |||
7 | TX_EMPTY | TX FIFO Empty High active. The flag of the interrupt flag that Parity errorTX FIFO empty. The interrupt will be cleaned when this bit is written 0 by master. | |||
3 | STOP_ERR | Stop Bit Error High active. The interrupt flag that Stop bit error. The interrupt will be cleaned when this bit is written 0 by master. | |||
4 | RX_FULL | RX FIFO Full High active. The interrupt flag that RX FIFO full. The interrupt will be cleaned when master reads out a data once. | |||
5 | RX_EMPTY | RX FIFO Empty High active. The flag that the RX FIFO empty | |||
6 | TX_FULL | TX FIFO Full High active. The flag that the TX FIFO full | |||
7 | TX_EMPTY | TX FIFO Empty High active. The flag of the interrupt that TX FIFO empty. The interrupt will be cleaned when master writes a data once. | |||
31:8 | RSV | Reserved |
4.6 RX FIFO Register (RX_FIFO, Addr = 5’h4)
Default Value: 0x00
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Register Bits
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Name
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Function Description
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7:0
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RX_FIFO
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Read Data Buffer
The depth is 4.
Store the data written to Receiver buffer register.
4.7 TX FIFO Register (TX_FIFO, Addr =5’h5)
Default Value: 0x00
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Register Bits
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Name
...
Function Description
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7:0
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TX_FIFO
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Write Data Buffer
The depth is 4.
Store the data written to Transmitter buffer register.
5 Functional Description
5.1 UART Structure
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Interface model: communicate with CPU, configure the UART.
FIFO: store data which will be transmitted or received
Transmit/Receive register: transmit or receive the data stored in the FIFO.
Baud rate occur: occur the clock for transmitter and receiver
5.2 UART Receiver FSM
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master writes a data once. | ||
31:8 | RSV | Reserved |
4.6 RX FIFO Register (RX_FIFO, Addr = 5’h4)
Default Value: 0x00
Register Bits | Name | Function Description |
7:0 | RX_FIFO | Read Data Buffer The depth is 4. Store the data written to Receiver buffer register. |
4.7 TX FIFO Register (TX_FIFO, Addr =5’h5)
Default Value: 0x00
Register Bits | Name | Function Description |
7:0 | TX_FIFO | Write Data Buffer The depth is 4. Store the data written to Transmitter buffer register. |
5 Functional Description
5.1 UART Structure
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Interface model: communicate with CPU, configure the UART.
FIFO: store data which will be transmitted or received
Transmit/Receive register: transmit or receive the data stored in the FIFO.
Baud rate occur: occur the clock for transmitter and receiver
5.2 UART Receiver FSM
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Current State | Function | Next Status | Jump Condition |
IDLE | Wait start signal. | SHIFT | Start bit detected right and receiver buffer register isn’t full |
IDLE | RX_EN enable or start bit not detected | ||
SHIFT | Receive data | STOP | Last data bit and parity disable |
PARITY | Last data bit and parity enable | ||
SHIFT | Not last data bit | ||
PARITY | Odd/even parity check | STOP | Parity check done |
STOP | Stop bit check | IDLE | Check right, then jump to IDLE Or check right wrong ,INT_B enable, then jump to IDLE |
5.3 UART Transmitter FSM
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Current State | Function | Next Status | Jump Condition | ||||
IDLE | Wait start signal. | SHIFT | Start bit detected right and receiver buffer register isn’t full | ||||
IDLE | RX_EN enable or start bit not detected | ||||||
SHIFT | Receive data | STOPfor transmitting | START | TX_FIFO is not empty | |||
IDLE | TX_FIFO is empty or TX_EN enable | ||||||
START | Transmit start bit | SHIFT | Transmit done | ||||
SHIFT | Transmit data | STOP_1BIT | Last data bit and parity disable | ||||
PARITY | Last data bit and parity enable | ||||||
SHIFT | Not last data bit | ||||||
PARITY | Odd/even parity check | STOP | Parity check donebit | STOP | Stop bit check | IDLE | Check right, then jump to IDLE Or check right wrong ,INT_B enable, then jump to IDLE |
5.3 UART Transmitter FSM
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Current State | Function | Next Status | Jump Condition |
IDLE | Wait for transmitting | START | TX_FIFO is not empty |
IDLE | TX_FIFO is empty or TX_EN enable | ||
START | Transmit start bit | SHIFT | Transmit done |
SHIFT | Transmit data | STOP_1BIT | Last data bit and parity disable |
PARITY | Last data bit and parity enable | ||
SHIFT | Not last data bit | ||
PARITY | Parity bit | STOP_1BIT | Finished the parity configuration |
STOP_1BIT | 1 stop bit | START | 1.5/2 stop bit disable |
STOP_HALFBIT | 1.5 stop bit enable | ||
STOP_2BIT | 2 stop bit enable | ||
STOP_HALFBIT | 1.5 stop bit | START | Finished the stop bit configuration |
STOP_2BIT | 2 stop bit | START | Finished the stop bit configuration |
5.4 FIFO
FIFO is very important to this design as all data are transferred by it. Following is the 2-pointer FIFO
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It is a 4X8-bit FIFO, so the width of both write pointer (WP) and read pointer (RP) are 3 bits. Read data once, RP adds one, while write data once, WP adds one.
When write, first write data, then move the WP pointer; when read, first read data, then move the RP pointer.
When WP = RP indicates FIFO is empty.
When WP [2] = (~RP [2]) and WP [1:0] = RP [1:0] shows this is a full FIFO
5.5 Timing Figures
Receive the serial data from RX
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Transmit the serial data to TX
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6 SOC 整合实现
6.1 UART 控制器IP设计实验项目的硬件平台实现
UART控制器IP核设计是AMBA APB总线接口，而我们FBIO Wrapper是AMBA AXI总线接口, 不能直接连接在一起，需要一个AXI2ABP 的Bridge进行连接；如下图所示：
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本实验以Plus1 7021 SOC实践平台配套的FPGA子板完成相关实验，实验采用loopback方式进行，即将UART控制器IP核设计的TX和RX对接即可;
FPGA子板的开发工具采用XILINX的Vivado集成开发环境(版本号为2018.3);为了方便将用户自己需要验证的IP方便连接到SOC系统中验证，本实验提供了相应的设计参考基础文件，如下
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设计案例与SP7021主板与FPGA子板脚位对应连接关系如下表所示：
1: 主板上的U20B接FPGA子板的J2(Pin脚对应，如 1-51...),提供主板上的Plus1 主芯片与FPGA的数据传输通道
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Design Demo | FPGA子板 | SP7021主板_1BIT | Finished the parity configuration | ||
STOP_1BIT | 1 stop bit | START | 1.5/2 stop bit disable | ||
STOP_HALFBIT | 1.5 stop bit enable | ||||
STOP_2BIT | 2 stop bit enable | ||||
STOP_HALFBIT | 1.5 stop bit | START | Finished the stop bit configuration | ||
STOP_2BIT | 2 stop bit | START | Finished the stop bit configuration | ||
5.4 FIFO
FIFO is very important to this design as all data are transferred by it. Following is the 2-pointer FIFO
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It is a 4X8-bit FIFO, so the width of both write pointer (WP) and read pointer (RP) are 3 bits. Read data once, RP adds one, while write data once, WP adds one.
When write, first write data, then move the WP pointer; when read, first read data, then move the RP pointer.
When WP = RP indicates FIFO is empty.
When WP [2] = (~RP [2]) and WP [1:0] = RP [1:0] shows this is a full FIFO
5.5 Timing Figures
Receive the serial data from RX
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Transmit the serial data to TX
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6 SOC integration
6.1 Hardware platform implementation of UART controller IP design experiment project
The UART controller IP core design is the AMBA APB bus interface, and our FBIO Wrapper is the AMBA AXI bus interface, which cannot be directly connected together, and requires an AXI2ABP Bridge to connect;
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This experiment uses the FPGA daughter board supporting the Plus1 7021 SOC practice platform to complete the relevant experiment. The experiment is carried out in loopback mode, which is to connect the TX and RX of the UART controller IP core design; The development tool of FPGA daughter board uses XILINX's Vivado integrated development environment (version number is 2018.3); in order to facilitate the connection of the user's own verification IP to the SOC system for verification, this experiment provides the corresponding design reference basic files, as follows
The corresponding connection between the design case and the pin connection of the SP7021 motherboard and FPGA daughter board is shown in the following table: 1: U20B on the main board is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the main board and the FPGA
Design Demo | FPGA daughter board | SP7021 mother board | |||
uart_apb | J2 | U1E | U20B | ||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | ||
| 1 | GND |
| 51 | GND |
| 2 | GND |
| 52 | GND |
FPGA_PAD[0] | 3 | B34_L24_N | T8 | 53 | FBIO_PAD_0 |
FPGA_PAD[43] | 4 | B34_L24_P | R8 | 54 | FBIO_PAD_1 |
| 5 | VIN |
| 55 | VCC(3.3V) |
| 6 | VCCIO34 |
| 56 | VCC(3.3V) |
FPGA_PAD[1] | 7 | B34_L21_N | V9 | 57 | FBIO_PAD_2 |
FPGA_PAD[42] | 8 | B34_L21_P | U9 | 58 | FBIO_PAD_3 |
FPGA_PAD[2] | 9 | B34_L18_N | N6 | 59 | FBIO_PAD_4 |
FPGA_PAD[41] | 10 | B34_L18_P | M6 | 60 | FBIO_PAD_5 |
FPGA_PAD[3] | 11 | B34_L22_N | U6 | 61 | FBIO_PAD_6 |
FPGA_PAD[40] | 12 | B34_L22_P | U7 | 62 | FBIO_PAD_7 |
FPGA_PAD[4] | 13 | B34_L20_N | V6 | 63 | FBIO_PAD_8 |
FPGA_PAD[39] | 14 | B34_L20_P | V7 | 64 | FBIO_PAD_9 |
FPGA_PAD[5] | 15 | B34_L23_N | T6 | 65 | FBIO_PAD_10 |
FPGA_PAD[38] | 16 | B34_L23_P | R7 | 66 | FBIO_PAD_11 |
FPGA_PAD[6] | 17 | B34_L10_N | V4 | 67 | FBIO_PAD_12 |
FPGA_PAD[37] | 18 | B34_L10_P | V5 | 68 | FBIO_PAD_13 |
FPGA_PAD[7] | 19 | B34_L19_P | R6 | 69 | FBIO_PAD_14 |
FPGA_PAD[36] | 20 | B34_L19_N | R5 | 70 | FBIO_PAD_15 |
FPGA_PAD[8] | 21 | B34_L8_P | U4 | 71 | FBIO_PAD_16 |
FPGA_PAD[35] | 22 | B34_L8_N | U3 | 72 | FBIO_TCLK |
FPGA_PAD[9] | 23 | B34_L9_N | V2 | 73 | FBIO_RCLK |
FPGA_PAD[34] | 24 | B34_L9_P | U2 | 74 | FBIO_PAD_17 |
FPGA_PAD[10] | 25 | B34_L7_N | V1 | 75 | FBIO_PAD_18 |
FPGA_PAD[33] | 26 | B34_L7_P | U1 | 76 | FBIO_PAD_19 |
FPGA_PAD[11] | 27 | B34_L13_P | N5 | 77 | FBIO_PAD_20 |
FPGA_PAD[32] | 28 | B34_L13_N | P5 | 78 | FBIO_PAD_21 |
FPGA_PAD[12] | 29 | B34_L12_P | T5 | 79 | FBIO_PAD_22 |
FPGA_PAD[31] | 30 | B34_L12_N | T4 | 80 | FBIO_PAD_23 |
FPGA_PAD[13] | 31 | B34_L11_N | T3 | 81 | FBIO_PAD_24 |
FPGA_PAD[30] | 32 | B34_L11_P | R3 | 82 | FBIO_PAD_25 |
FPGA_PAD[29] | 33 | B34_L14_P | P4 | 83 | FBIO_PAD_26 |
FPGA_PAD[28] | 34 | B34_L14_N | P3 | 84 | FBIO_PAD_27 |
FPGA_PAD[14] | 35 | B34_L16_N | N4 | 85 | FBIO_PAD_28 |
FPGA_PAD[27] | 36 | B34_L16_P | M4 | 86 | FBIO_PAD_29 |
FPGA_PAD[15] | 37 | B34_L17_N | T1 | 87 | FBIO_PAD_30 |
FPGA_PAD[26] | 38 | B34_L17_P | R1 | 88 | FBIO_PAD_31 |
FPGA_PAD[16] | 39 | B34_L15_N | R2 | 89 | FBIO_PAD_32 |
FPGA_PAD[25] | 40 | B34_L15_P | P2 | 90 | FBIO_PAD_33 |
FPGA_PAD[17] | 41 | B34_L3_N | N1 | 91 | FBIO_PAD_34 |
FPGA_PAD[24] | 42 | B34_L3_P | N2 | 92 | FBIO_PAD_35 |
FPGA_PAD[18] | 43 | B34_L1_N | M1 | 93 | FBIO_PAD_RSTB |
FPGA_PAD[23] | 44 | B34_L1_P | L1 | 94 | EXT0_INT |
| 45 | VCCIO34 |
| 95 | VCC(3.3V) |
| 46 | VIN |
| 96 | VCC(3.3V) |
FPGA_PAD[19] | 47 | B34_L4_P | M3 | 97 | EXT1_INT |
FPGA_PAD[20] | 48 | B34_L4_N | M2 | 98 |
|
| 49 | GND |
| 99 | GND |
| 50 | GND |
| 100 | GND |
2: 主板上的U20A接FPGA子板的J1(Pin脚以一对应，如 U20A on the motherboard is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...)，经由J17将FPGA Bank 35的42 , and the 42 pin IO (3.3v) 扩展出来，供用户使用of FPGA Bank 35 is extended via J17 for users to use
...
Design Demo | FPGA子板 | SP7021主板FPGA daughter board | SP7021 mother board | |||||||
uart_apb | J1 | U1F | U20A | J17 | ||||||
Top Port Name | Schematic Name | FPGA I/O | Schematic Name | Schematic Name | ||||||
| 1 | GND |
| 1 | GND | 3 | GND | |||
| 2 | GND |
| 2 | GND | 4 | GND | |||
FPGA_TX | 3 | B35_L23_N | K1 | 3 | B35_L23_N | 5 | B35_L23_N | |||
| 4 | B35_L23_P | K2 | 4 | B35_L23_P | 6 | B35_L23_P | |||
| 5 | VIN |
| 5 | VIN | 1 | VCC | |||
| 6 | VCCIO35 |
| 6 | VCCIO35 | 2 | VCC | |||
FPGA_RX | 7 | B35_L15_N | G2 | 7 | B35_L15_N | 7 | B35_L15_N | |||
| 8 | B35_L15_P | H2 | 8 | B35_L15_P | 8 | B35_L15_P | |||
| 9 | B35_L13_N | F3 | 9 | B35_L13_N | 9 | B35_L13_N | |||
| 10 | B35_L13_P | F4 | 10 | B35_L13_P | 10 | B35_L13_P | |||
| 11 | B35_L12_N | D3 | 11 | B35_L12_N | 11 | B35_L12_N | |||
| 12 | B35_L12_P | E3 | 12 | B35_L12_P | 12 | B35_L12_P | |||
| 13 | B35_L22_P | J3 | 13 | B35_L22_P | 13 | B35_L22_P | |||
| 14 | B35_L22_N | J2 | 14 | B35_L22_N | 14 | B35_L22_N | |||
| 15 | B35_L17_N | G1 | 15 | B35_L17_N | 15 | B35_L17_N | |||
| 16 | B35_L17_P | H1 | 16 | B35_L17_P | 16 | B35_L17_P | |||
| 17 | B35_L18_N | E1 | 17 | B35_L18_N | 17 | B35_L18_N | |||
| 18 | B35_L18_P | F1 | 18 | B35_L18_P | 18 | B35_L18_P | |||
| 19 | B35_L14_N | D2 | 19 | B35_L14_N | 19 | B35_L14_N | |||
| 20 | B35_L14_P | E2 | 20 | B35_L14_P | 20 | B35_L14_P | |||
| 21 | B35_L16_P | C2 | 21 | B35_L16_P | 21 | B35_L16_P | |||
| 22 | B35_L16_N | C1 | 22 | B35_L16_N | 22 | B35_L16_N | |||
| 23 | B35_L9_N | A1 | 23 | B35_L9_N | 23 | B35_L9_N | |||
| 24 | B35_L9_P | B1 | 24 | B35_L9_P | 24 | B35_L9_P | |||
| 25 | B35_L10_P | B3 | 25 | B35_L10_P | 25 | B35_L10_P | |||
| 26 | B35_L10_N | B2 | 26 | B35_L10_N | 26 | B35_L10_N | |||
| 27 | B35_L8_N | A3 | 27 | B35_L8_N | 27 | B35_L8_N | |||
| 28 | B35_L8_P | A4 | 28 | B35_L8_P | 28 | B35_L8_P | |||
| 29 | B35_L11_N | D4 | 29 | B35_L11_N | 29 | B35_L11_N | |||
| 30 | B35_L11_P | D5 | 30 | B35_L11_P | 30 | B35_L11_P | |||
| 31 | B35_L3_N | A5 | 31 | B35_L3_N | 31 | B35_L3_N | |||
| 32 | B35_L3_P | A6 | 32 | B35_L3_P | 32 | B35_L3_P | |||
| 33 | B35_L2_N | B6 | 33 | B35_L2_N | 33 | B35_L2_N | |||
| 34 | B35_L2_P | B7 | 34 | B35_L2_P | 34 | B35_L2_P | |||
| 35 | B35_L7_N | B4 | 35 | B35_L7_N | 35 | B35_L7_N | |||
| 36 | B35_L7_P | C4 | 36 | B35_L7_P | 36 | B35_L7_P | |||
| 37 | B35_L1_N | C5 | 37 | B35_L1_N | 37 | B35_L1_N | |||
| 38 | B35_L1_P | C6 | 38 | B35_L1_P | 38 | B35_L1_P | |||
| 39 | B35_L5_N | E5 | 39 | B35_L5_N | 39 | B35_L5_N | |||
| 40 | B35_L5_P | E6 | 40 | B35_L5_P | 40 | B35_L5_P | |||
| 41 | B35_L6_N | D7 | 41 | B35_L6_N | 41 | B35_L6_N | |||
| 42 | B35_L6_P | E7 | 42 | B35_L6_P | 42 | B35_L6_P | |||
| 43 | B35_L19_P | G6 | 43 | B35_L19_P | 43 | B35_L19_P | |||
| 44 | B35_L19_N | F6 | 44 | B35_L19_N | 44 | B35_L19_N | |||
| 45 | VCCIO35 |
| 45 | VCCIO35 |
|
| |||
| 46 | VIN |
| 46 | VIN |
|
| |||
| 47 | B35_L4_N | C7 | 47 | B35_L4_N | 45 | B35_L4_N | |||
| 48 | B35_L4_P | D8 | 48 | B35_L4_P | 46 | B35_L4_P | |||
| 49 | GND |
| 49 | GND |
|
| |||
| 50 | GND |
| 50 | GND |
|
| |||
6.2
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Implementation of System Software Platform for UART Controller IP Design Experiment Project
在IDE 环境中如下图所示，选择sp7021工程名，单击鼠标右键在弹出的菜单中选Copy
...
#endif // __FPGAINT_H__
定义了UART控制IP相关寄存器
程序代码运行
在Plus1 IDE环境中compile后，下载到平台，在terminal窗口看到如下信息
...