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This experiment uses the FPGA daughter board and extended test daughter board supporting the Plus1 7021 practice platform to complete the relevant experiments. The development tool of the FPGA daughter board uses the XILINX Vivado integrated development environment (version number 2018.3); in order to facilitate the user to verify the IP It is convenient to connect to the SOC system for verification. This experiment provides the corresponding basic files, as follows

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5.6.1 Vivado software installation

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    There are two input clocks for the FPGA daughter board used in this experiment: All the way is the 25M clock GCLK that comes with the FPGA board. There are relevant constraints in the fpga_top.xdc constraint file: create_clock -period 40.000 -name GCLK -waveform {0.000 20.000} [get_ports GCLK] After accessing FPGA, use its internal PLL IP to generate the FBIO TX clock io_clk, reference clock ref_clk and system clock sysclk required by the project; the corresponding source file structure is as followsImage Removed

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The other way is the FBIO RX 36M clock of the FBIO BUS connected to the FPGA; there are related constraints in the fpga_top.xdc constraint file: create_clock -period 27.000 -name rclk -waveform {0.000 12.500} [get_ports {FPGA_PAD [35]}] The following introduces the use of its internal PLL IP after GCLK is connected to the FPGA to generate the clock required by the project. Refer to the figure below, double-click the red box to start the PLL setting operation

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