Page Comparison

...

16.4 UART2 Modem Control Register (uart2 mcr)

Address: 0x9C000810Reset0x9C000810

Reset: 0x0000

Field Name	Bit	Access	Description
RSV	15:8	RO	Reserved
AT	7	RW	AUTO CALIBRATE0: No auto calibrate (or auto-calibration finished)(default).1: Start baud-rate auto calibration. Calibration will stop after receive expected token (ASCII 'a' or 'A').
AC	6	RW	AUTO CTS mode0: Disable CTS detection, TX FIFO sends out data al- ways(default).1: Enable CTS detection, only send data when CTS B is active (low).
AR	5	RW	AUTO RTS mode0: UART RTS B is controlled by RTS register(default).1: UART RTS B is controlled by receive FIFO status.
LB	4	RW	MCR loop-back mode0: Disable loop-back (normal function)(default).1: Loop-back mode. In loop-back mode:RXD, DSR, CTS = TXD, DTR, RTS. RI, DCD = RI OUT, DCD OUT. External output TXD = mark (high).External output DTR B,RTS B = inactive (high).
RI	3	RW	Ring-indicator register 0: UART RI inactive (output low)(default). 1: UART RI active (output high).
DCD	2	RW	Data carrier detect register 0: UART DCD B inactive (output high)(default). 1: UART DCD B active (output low).
RTS	1	RW	Request to send register (not used in AUTORTS mode) 0: UART RTS B inactive (output high)(default). 1: UART RTS B active (output low).
DTS	0	RW	Data terminal ready register 0: UART DTR B inactive (output high)(default). 1: UART DTR B active (output low).

16.5 UART2 Clock Divider Low Register (uart2 div l)

Address: 0x9C000814Reset0x9C000814

Reset: 0x903A

UART2 clock divisor for 16x over-sampling clock (low part)

...

16.6 UART2 Clock Divider High Register (uart2 div h)

Address: 0x9C000818Reset0x9C000818

Reset: 0x0000

Field Name	Bit	Access	Description
RSV	15:8	RO	Reserved
divisor[15:8]	7:0	RW	System clock divisor MSB Refer to system clock divisor MSB for more details

...

16.7 UART2 Interrupt Status/Control register (uart2 isc)
Address: 0x9C00081C
Reset: 0x0000

Field Name	Bit	Access	Description
RSV	15:8	RO	Reserved
MSM	7	RW	Modem Status interrupt Mask0: INT disable(default). 1: INT enable.
LSM	6	RW	Line Status interrupt Mask0: INT disable(default). 1: INT enable.
RXM	5	RW	RX interrupt Mask0: INT disable(default). 1: INT enable.
TXM	4	RW	TX interrupt Mask0: INT disable(default). 1: INT enable.
MS	3	RU	Modem status interrupt flag This bit is set when any of DT DSR, DT CTS, DT DCD, or TE RI is one and MSR interrupt is enabled. 0: No modem status interrupt issued(default). 1: Modem status interrupt issued.
LS	2	RU	Line status interrupt flag This bit is asserted when and of PE, FE, BC, OE condition occurred and LS interrupt is enable. 0: No line status interrupt issued(default). 1: Line status interrupt issued.
RX INT	1	RU	RX FIFO NOT EMPTY interrupt flag. This bit is asserted when RX FIFO is not empty and RX interrupt enable. 0: No RX interrupt issued(default). 1: RX interrupt issued.
TX INT	0	RU	TX FIFO EMPTY interrupt flag. This bit is asserted when TX FIFO is empty and TX interrupt is enable. 0: No TX interrupt issued(default). 1: TX interrupt issued.

16.8 UART2 TX Residue (uart2 tx residue)

Address: 0x9C000820Reset0x9C000820

Reset: 0x0000

Field Name	Bit	Access	Description
RSV	15:7	RO	Reserved
tx residue	6:0	RO	tx residue, TX FIFO flushRead to get the remainder characters in the TX FIFO. Write zero to flush TX FIFO, and write other values has no effect.

...

16.9 UART2 RX Residue (uart2 rx residue)

Address: 0x9C000824Reset0x9C000824

Reset: 0x0000

Field Name	Bit	Access	Description
RSV	15:7	RO	Reserved
rx residue	6:0	RO	rx residue, RX FIFO flushRead to get the remainder characters in the RX FIFO. Write zero to flush RX FIFO, and write other values has no effect.

...

16.10 UART2 RX FIFO Threshold (uart2 rx threshold)

Address: 0x9C000828Reset0x9C000828

Reset: 0x0000

Field Name	Bit	Access	Description
RSV	15:12	RO	Reserved
RXFIFO THRESHOLD	11:4	RW	RXFIFO Threshold ValueSet the remainder space in the RXFIFO.If the remaining space is less than RXFIFO THRESHOLD, it would assert interrupt when RXFIFO Threshold is enabled. unit : byte.
RSV	3:1	RO	Reserved
RXFIFO THR ENABLE	0	RW	RXFIFO Threshold Enable 0 : disable threshold control for RXFIFO(default). 1 : enable threshold control for RXFIFO.

...

16.11 UART2 clock baud rate select (uart2 clk baud sel)

Address: 0x9C00082C
Reset: 0x0001

...

RGST Table Group 273 GDMA: General DMA (HWUA_GDMA0)

273.0 DMA HW VER (dma hw ver)
Address: 0x9C008880Reset0x9C008880

Reset: 0x0179 1000

Field Name	Bit	Access	Description
DMA HW VER	31:0	RO	Hardware VersionA constant, usually stands for hw delivery date, such as 32'h01791000.

273.1 DMA CONFIG (dma config)
Address: 0x9C008884Reset0x9C008884

Reset: 0x0000 0004

Field Name	Bit	Access	Description
Reserved	31:9	RO	Reserved
DMA GO	8	RUW	DMA GO SignalWrite 1 to trigger DMA hardware, self clear to zero when current operation has been finished.
Reserved	7:3	RO	Reserved
NON BUF MODE	2	RW	GDMA write command bufferable 0x0: all write command is bufferable 0x1: all write command is non-buffer(default) Valid when DMA_GO been set to1, and can not be changed when DMA_GO assert.
SAME SLAVE	1	RW	GDMA access same slave 0x0: access different slave in SG mode (like CBDMA&DRAM at the same time)(default) 0x1: access same slave in SG mode Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.
DMA MODE	0	RW	Set DMA Mode 0x0: DMA_READ(read data from main memory to internal SRAM)(default) 0x1: DMA_WRITE(write data from internal SRAM to main memory) Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.

273.2 DMA LENGTH (dma length)
Address: 0x9C008888Reset0x9C008888

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:25	RO	Reserved
DMA LENGTH	24:0	RW	Set DMA LengthDMA read and write function support length. Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.

273.3 DMA ADR (dma adr)
Address: 0x9C00888CReset0x9C00888C

Reset: 0x0000 0000

Field Name	Bit	Access	Description
DMA SRC ADR	31:0	RW	DMA Source Address DMA WRITE: indicate write to which main memory address DMA READ: indicate read from which main memory address Valid when DMA_GO been set to 1, and can not be changed when DMA_GO assert.

273.4 DMA PORT MUX (dma port mux)
Address: 0x9C008890Reset0x9C008890

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:1	RO	Reserved
PORT MUX	0	RW	PORT MUX use to select PORT, ex. UART0, UART1.

273.5 DMA INT FLAG (dma int flag)
Address: 0x9C008894Reset0x9C008894

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:7	RO	Reserved
LENGTH0 REG	6	W1C	Length is zero flag In SG Mode: If RUN_LLI_INDEX length is zero, the LENGTH0_REG will 1. In Normal Mode: If length is zero, the LENGTH0_REG will be 1.
THRESHOLD REG	5	W1C	Threshold flag In SG Mode: When RUN_LLI_INDEX=THRESHOLD_LLI_INDEX and NUM=THRESHOLD_NUM, the interrupt will occurs. In Normal Mode: When NUM=THRESHOLD_NUM, the interrupt will occurs.
IP TIMEOUT REG	4	W1C	Peripheral IP TimeoutWhen GDMA wait Peripheral IP too long will set HIGH, depend on IP_TIMEOUT_DEF_WRITE and IP_TIMEOUT_DEF_READ.
GDMA TIMEOUT REG	3	W1C	GDMA TimeoutWhen Peripheral IP wait GDMA too long will set HIGH, depend on GDMA_TIMEOUT_DEF_WRITE and GDMA_TIMEOUT_DEF_READ.
WRITE BYTE ENABLE ERROR REG	2	W1C	Peripheral IP WRITE_BYTE_EN error flagWRITE_BYTE_EN not meet the protocol.
WRITE CNT	1	W1C	Peripheral IP DATA CNT error flagData Count error.
DMA DONE FLAG	0	W1C	DMA DONEIf DMA done, this bit will be assert. Write 1 to clear.

273.5 DMA INT FLAG (dma int flag)
Address: 0x9C008894Reset0x9C008894

Reset: 0x0000 0000

Field Name	Bit	Access	Description
Reserved	31:7	RO	Reserved
LENGTH0 REG	6	W1C	Length is zero flag In SG Mode: If RUN_LLI_INDEX length is zero, the LENGTH0_REG will 1. In Normal Mode: If length is zero, the LENGTH0_REG will be 1.

RGST Table Group 275 UADMA

275.0 RF DMA0 ENABLE SEL (rf dma0 enable sel)
Address: 0x9C008980Reset0x9C008980

Reset: 0x0000 0000

Field Name	Bit	Access	Description
D0INT	31	RU	DMA0 INT 0: Clear by DMA INT CLR(default). 1: Clear INT State,DMA STATE wait for DMA GO.
RSV	30:21	RO	Reserved
D0OFC	20	RW	DMA0 OVER FLOW CONFIG judge the fifo threshold, stop the dma access or not when interrupt is occur.
RSV	19	RO	Reserved
D0MI	18:12	RW	DMA0 MSI ID DMA0 setting MSI ID.
RSV	11	RO	Reserved
D0SU	10:8	RW	DMA0 SELECT UART DMA0 select UA# RN, # is from 0 to 5.
D0SRB	7	RW	DMA0 SOFT RESET. 0: active reset and back to initial-DMA. DMA WR ADDR[31:0] = DMA START ADDR[31:0]. DMA DATABYTES[15:0] = 0. DMA SW RST B usage steps: a. UADMA AUTO ENABLE == 0. b. When DMA DEBUG INFO == c dma stage[3:0] is 0. c. Set DMA SW RSTB == 0 - 1. d. initial UADMA state. 1: normal work(default).
D0INIT	6	RW	DMA0 INITIAL BEFORE DMA FIRST GO, It NEED SETTING INITIAL SETTING. 0: DMA not initial(default). 1: DMA INIT, write 1 to initialize DMA and followed by writing 0 to finish initialization. After initializedDMA WR ADDR[31:0]==DMA START ADDR[31:0] DMA RD ADDR[31:0]==DMA START ADDR[31:0]
D0GO	5	RU	DMA0 GO 0: it will return to 0 automatically after triggered to 1(default). 1: DMA continue/start
D0AE	4	RW	DMA0 AUTO ENABLE 0: Disable DMA0 Engine(default). 1: Enable DMA0 Engine.
D0TIE	3	RW	DMA0 TIMEOUT INT EN 0: time out no issue interrupt(default). 1: time out issue interrupt.
D0PSD	2	RW	DMA0 P SAFE DISABLE 0: when every pbus traffic issue write flush and msi command, it's say that the data write into DRAM will be send MSI cmd(default). 1: when data bytes reach to thread x 2, issue write flush and msi command.
D0PS	1	W	DMA0 PBUS DATA SWAP 0:PBUS DATA[15:0] == "Byte0 , Byte1"(default). 1:PBUS DATA[15:0] == "Byte1 , Byte0".
D0EN	0	RW	DMA0 ENABLE 0: Disable UA# Data to DMA0(default). 1: Enable UA# Data to DMA0.

275.1 RF DMA0 START ADDR (rf dma0 start addr)

Address: 0x9C008984Reset0x9C008984

Reset: 0x0

Field Name	Bit	Access	Description
D0SA	31:0	RW	DMA0 Start Address

...

275.2 RF DMA0 TIMEOUT SET (rf dma0 timeout set)

Address: 0x9C008988Reset0x9C008988

Reset: 0x0

Field Name	Bit	Access	Description
D0TD	31:0	RW	DMA0 TIMEOUT DEF Timer for RX data time in DATA_ST. When Timer >= DMA TIMEOUT DEF, datta will auto send to PBUS without waiting for fill-up 8 bytes.

...

275.4 RF DMA0 WR ADR (rf dma0 wr adr)

Address:0x9C008990

Reset:0x0

Field Name	Bit	Access	Description
D0WA	31:0	RO	DMA0 Write Address DMA next write address. It will update by PBUS accept cmd and data, <no-data in location>.

...

275.5 RF DMA0 RD ADR (rf dma0 rd adr)

Address: 0x9C008994Reset0x9C008994

Reset: 0x0

Field Name	Bit	Access	Description
D0RA	31:0	RW	DMA0 Read Address DMA(CPU) read out address. <It had read>.

275.6 RF DMA0 LENGTH THR (rf dma0 length thr)

Address: 0x9C008998Reset0x9C008998

Reset: 0x8

Field Name	Bit	Access	Description
D0LEN	31:16	RW	DMA0 LENGTH Data Range, # of bytes in DMA Space , 2ˆpower and < 1.
D0THD	15:0	RW	DMA0 THREADHOLD DMA threshold for access PBUS. When #DMA LENGTH[15:0] - #DMA DATABYTES <=DMA THREADHOLD, pause DMA StateMachine and issue DMA INT. DMA will access until redundant 16 Bytes.

...

275.7 RF DMA0 END ADDR (rf dma0 end addr)

Address: 0x9C00899C
Reset: 0x0

...

275.8 RF DMA0 DATABYTES (rf dma0 databytes)

Address: 0x9C0089A0Reset0x9C0089A0

Reset: 0x0

Field Name	Bit	Access	Description
D0DB	15:0	RO	DMA0 DATABYTESData Bytes in DMA0 SPACE

...

275.17 RF DMA1 START ADDR (rf dma1 start addr)

Address: 0x9C0089C4Reset0x9C0089C4

Reset: 0x0

Field Name	Bit	Access	Description
D1SA	31:0	RW	DMA1 Start Address

...

275.18 RF DMA1 TIMEOUT SET (rf dma1 timeout set)

Address: 0x9C0089C8Reset0x9C0089C8

Reset: 0x0

Field Name	Bit	Access	Description
D1TD	31:0	RW	DMA1 TIMEOUT DEF Timer for RX data time in DATA ST. When Timer >= DMA TIMEOUT DEF, datta will auto send to PBUS without waiting for fill-up 8 bytes.

...

275.20 RF DMA1 WR ADR (rf dma1 wr adr)

Address: 0x9C0089D0Reset0x9C0089D0

Reset: 0x0

Field Name	Bit	Access	Description
D1WA	31:0	RO	DMA1 Write Address DMA next will write address. It will update by PBUS accept cmd and data, <no-data in location>.

...

275.21 RF DMA1 RD ADR (rf dma1 rd adr)

Address: 0x9C0089D4Reset0x9C0089D4

Reset: 0x0

Field Name	Bit	Access	Description
D1RA	31:0	RW	DMA1 RD ADDR DMA(CPU) read out address. <It had read>.

...

275.22 RF DMA1 LENGTH THR (rf dma1 length thr)

Address: 0x9C0089D8Reset0x9C0089D8

Reset: 0x8

Field Name	Bit	Access	Description
D1LEN	31:16	RW	DMA1 LENGTH Data Range, # of bytes in DMA Space , 2ˆpower and < 1.
D1THD	15:0	RW	DMA1 THREADHOLD DMA threshold for access PBUS. When #DMA LENGTH[15:0] - #DMA DATABYTES <=DMA THREADHOLD, pause DMA StateMachine and issue DMA INT. DMA will access until redundant 16 Bytes.

...

275.23 RF DMA1 END ADDR (rf dma1 end addr)

Address: 0x9C0089DC
Reset: 0x0

...

275.24 RF DMA1 DATABYTES (rf dma1 databytes)

Address: 0x9C0089E0Reset0x9C0089E0

Reset: 0x0

Field Name	Bit	Access	Description
D1DB	15:0	RO	DMA1 DATABYTESData Bytes in DMA1 SPACE.

...

RGST Table Group 276 HW_BUF_UA

276.0 GDMA0 ENABLE (hw buf ua gdma0 enable)
Address: 0x9C008A00Reset0x9C008A00

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RCGDMA0EN	31	RC	REDO ENABLEAfter the error interrupt that HW_BUF_UA need to redo by CPU at DEBUG mode.
RSV	30:3	RO	Reserved
GDMA0RDEN	2	RW	GDMA0 READ ENABLEDetermine the GDMA0 read access when read enable is assert.
GDMA0WREN	1	RW	GDMA0 WRITE ENABLEDetermine the GDMA0 write access when write enable is assert.
GDMA0DEN	0	RW	GDMA0 DEBUG ENABLEDetermine the HW_BUF_UA access in debug mode when enable is assert.

276.1 GDMA0 SEL UARTX (hw buf ua gdma0 uart select)
Address: 0x9C008A04Reset0x9C008A04

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RSV	31:19	RO	Reserved
GDMA0SELUAWR	18:16	RW	GDMA0 SEL UARTX WRIf want access UA0, should setting the select[18:16] be 3'h0. 0x0:UART0 0x1:UART1 0x2:UART2 0x3:UART3 0x4:UART4
RSV	15:3	RO	Reserved
GDMA0SELUARD	2:0	RW	GDMA0 SEL UARTX RDIf want access UA0, should setting the select[2:0] be 3'h0. 0x0:UART0 0x1:UART1 0x2:UART2 0x3:UART3 0x4:UART4

276.2 GDMA0 START ADDR (hw buf ua gdma0 start address)
Address: 0x9C008A08Reset0x9C008A08

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA0SADR	31:0	RW	GDMA0 START ADDRThe ring buffer start addr that mapping to DRAM.

276.3 GDMA0 END ADDR (hw buf ua gdma0 end address)
Address: 0x9C008A0CReset0x9C008A0C

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA0EADR	31:0	RW	GDMA0 END ADDRThe ring buffer end addr that mapping to DRAM.

276.4 GDMA0 WRITE ADDR (hw buf ua gdma0 write address)
Address: 0x9C008A10Reset0x9C008A10

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA0WADR	31:0	RW	GDMA0 WRITE ADDRThe write address means that CPU write data address.

276.5 GDMA0 READ ADDR (hw buf ua gdma0 read address)
Address: 0x9C008A14Reset0x9C008A14

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA0RADR	31:0	RW	GDMA0 READ ADDRThe read address means that CPU read data address.

276.6 GDMA0 FULL EMPTY (hw buf ua gdma0 status)
Address: 0x9C008A18Reset0x9C008A18

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RSV	31:2	RO	Reserved
GDMA0EMP	1	RU	BUFFER EMPTYBuffer on DRAM status is empty
GDMA0FUL	0	RU	BUFFER FULLBuffer on DRAM status is full

276.7 GDMA0 TIMER UNIT (hw buf ua gdma0 timer unit)
Address: 0x9C008A1CReset0x9C008A1C

Reset: 0x0000 6978

Field Name	Bit	Access	Description
GDMA0TU	31:0	RW	GDMA0 TIMER UNITIn HW_BUF_UA, the TIMER_UNIT has default value that is 1ms on 27MHz.

276.8 GDMA0 TIMER COUNT (hw buf ua gdma0 timer count)
Address: 0x9C008A20Reset0x9C008A20

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA0TC	31:0	RW	GDMA0 TIMER COUNTThe TIMER_COUNT is count by TIMER count to TIMER_UNIT

276.9 GDMA0 SW RESET DONE (hw buf ua gdma0 sw reset done)
Address: 0x9C008A24Reset0x9C008A24

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RSV	31:1	RO	Reserved
GDMA0SRD	0	RO	GDMA0 SW RESET DONEWhen occur error interrupt, CPU need to set SW_RESET that check the transaction is done or not between GDMA and bus termination.

276.16 GDMA10 ENABLE (hw buf ua gdma1 enable)
Address: 0x9C008A40Reset0x9C008A40

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RCGDMA1EN	31	RC	REDO ENABLEAfter the error interrupt that HW_BUF_UA need to redo by CPU at DEBUG mode.
RSV	30:3	RO	Reserved
GDMA1RDEN	2	RW	GDMA1 READ ENABLEDetermine the GDMA1 read access when read enable is assert.
GDMA1WREN	1	RW	GDMA1 WRITE ENABLEDetermine the GDMA1 write access when write enable is assert.
GDMA1DEN	0	RW	GDMA1 DEBUG ENABLEDetermine the HW_BUF_UA access in debug mode when enable is assert.

276.17 GDMA1 SEL UARTX (hw buf ua gdma1 uart select)
Address: 0x9C008A44Reset0x9C008A44

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RSV	31:19	RO	Reserved
GDMA1SELUAWR	18:16	RW	GDMA1 SEL UARTX WRIf want access UA0, should setting the select[18:16] be 3'h0. 0x0:UART0 0x1:UART1 0x2:UART2 0x3:UART3 0x4:UART4
RSV	15:3	RO	Reserved
GDMA1SELUARD	2:0	RW	GDMA1 SEL UARTX RDIf want access UA0, should setting the select[2:0] be 3'h0. 0x0:UART0 0x1:UART1 0x2:UART2 0x3:UART3 0x4:UART4

276.18 GDMA1 START ADDR (hw buf ua gdma1 start address)
Address: 0x9C008A48Reset0x9C008A48

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA1SADR	31:0	RW	GDMA1 START ADDRThe ring buffer start addr that mapping to DRAM.

276.19 GDMA1 END ADDR (hw buf ua gdma1 end address)
Address: 0x9C008A4CReset0x9C008A4C

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA1EADR	31:0	RW	GDMA1 END ADDRThe ring buffer end addr that mapping to DRAM.

276.20 GDMA1 WRITE ADDR (hw buf ua gdma1 write address)
Address: 0x9C008A50Reset0x9C008A50

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA1WADR	31:0	RW	GDMA1 WRITE ADDRThe write address means that CPU write data address.

276.21 GDMA1 READ ADDR (hw buf ua gdma1 read address)
Address: 0x9C008A54Reset0x9C008A54

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA1RADR	31:0	RW	GDMA1 READ ADDRThe read address means that CPU read data address.

276.22 GDMA1 FULL EMPTY (hw buf ua gdma1 status)
Address: 0x9C008A58Reset0x9C008A58

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RSV	31:2	RO	Reserved
GDMA1EMP	1	RU	BUFFER EMPTYBuffer on DRAM status is empty
GDMA1FUL	0	RU	BUFFER FULLBuffer on DRAM status is full

276.23 GDMA1 TIMER UNIT (hw buf ua gdma1 timer unit)
Address: 0x9C008A5CReset0x9C008A5C

Reset: 0x0000 6978

Field Name	Bit	Access	Description
GDMA1TU	31:0	RW	GDMA1 TIMER UNITIn HW_BUF_UA, the TIMER_UNIT has default value that is 1ms on 27MHz.

276.24 GDMA1 TIMER COUNT (hw buf ua gdma1 timer count)
Address: 0x9C008A60Reset0x9C008A60

Reset: 0x0000 0000

Field Name	Bit	Access	Description
GDMA1TC	31:0	RW	GDMA1 TIMER COUNTThe TIMER_COUNT is count by TIMER count to TIMER_UNIT

276.25 GDMA1 SW RESET DONE (hw buf ua gdma1 sw reset done)
Address: 0x9C008A64Reset0x9C008A64

Reset: 0x0000 0000

Field Name	Bit	Access	Description
RSV	31:1	RO	Reserved
GDMA1SRD	0	RO	GDMA1 SW RESET DONEWhen occur error interrupt, CPU need to set SW_RESET that check the transaction is done or not between GDMA and bus termination.

...

Versions Compared

Old Version 11

New Version 12

Key