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changes.mady.by.user edwin.chiu

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Field Name

Bit

Access

Description

Reserved

31:16

RO

RESERVED

Reserved

15:11

RO

RESERVED

dmadst

10:8

RW

DMA Destination Selection
0x0: (default)
0x1: SDRAM
0x2: Flash Memory

others: reserved
Note: when read data from card, user shall select '1'; when write data to card, select '2'

Reserved

7

RO

RESERVED

dmasrc

6:4

RW

DMA Source Selection
0x0: (default)
0x1: SDRAM
0x2: Flash Memory

others: reserved
Note: when read data from card, user shall select '2'; when write data to card, select '1'

Reserved

3

RO

RESERVED

MediaType

2:0

RW

The Storage Media Type Selection
0x0 : None, low power mode(default)
0x6 : SD memory card (SD/MMC/SDIO)
0x7 : Memory Stick (MS/MSPro Card)

others : reserved

...

Field Name

Bit

Access

Description

Reserved31:16RORESERVED
CARD CTL PAGE CNT15:0RO

Page Number that CARD CTL is Reading/Writing Currently
If SDRAM write to Card, it shows that CARD CTL is carrying the page data in CARD CTL PAGE CNT to flash memory.
If SDRAM read from Card, it show that CARD CTL is carrying the page data in CARD CTL PAGE CNT from flash memory.



118.2 Length of SDRAM Sector 0 (sdram sector 0 size)
Address: 0x9C003B08
Reset: 0x0000 FFFF


Field Name

Bit

Access

Description

Reserved31:16RORESERVED

SDRAM SECTOR 0 SIZE

15:0

RW

The Length of Sector 0 in SDRAM

The actual size equals SDRAM SECTOR 0 SIZE + 1, the unit is page(512 bytes)

Note: this sector register can only used in HW DMA mode

default is '0xffff'

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Field Name

Bit

Access

Description

HWSD CMD13 RCA31:16RWThe Relative Card Address
This register is used for the argument of cmd13 when
HW DMA EN & HW SD CMD13 EN equals '1'
Reserved15:14RORESERVED
HW BLOCK NUM13:12RWHW DMA Block Number
The actual Blcok number is (HW BLOCK NUM+1).
dmastart11WOHW DMA Start
HW DMA EN=1, write 1 to this bit will trigger a hardware
speedup multi page DMA data transfer cycle.
dmaidle10RWDMA Idle
0: Normal state(default)
1: Idle state (reset the DMA operation)
HW DMA RST9WOHW DMA Rst
Write 1 to this field will reset the HW DMA(HW State Ma-
chine) function
STOP DMA FLAG8RUWHW DMA Stop
Write 1 to this field will trigger Stop HW DMA function, and this bit will be cleared when sdrst ,HW DMA RST or dmacmpsclr reg
Reserved7RORESERVED
HW SD CMD13 EN6RWMulti Block Transfer CMD13 Enable
High active,it is suggested that setting this bit to 1, default is '0', only multi block transfer use

HW SD DMA TYPE

5:4

RW

SD Hardware Type of DMA Mode
0x1 : Signal block read or write
0x2 : Multi block read or write others : reserved(default)

HW SD HCSD EN

3

RW

High Capacity Card enable
0 : Standard Card(default)
1 : High Capacity Card

Reserved

2

RO

RESERVED

HW DMA EN

1

RW

HW DMA Function Enable
0: Disable HW DMA mode(default)
1: Enable HW DMA mode

Reserved

0

RO

RESERVED



118.5 Clock Gated Disable (CARD GCLK DISABLE)
Address: 0x9C003B14
Reset: 0x0


Field Name

Bit

Access

Description

Reserved31:16RORESERVED
Reserved15:12RORESERVED
REG CARD REG FREE11RWGCLKDIVCARD CARD REG Free run
set this bit to 1 will make GCLKDIVCARD CARD REG
clock free run,no longer clock gating
REG DMA REG FREE10RWGCLKDIVCARD DMA REG Free run
have the same usage with GCLKDIVCARD CARD REG
Reserved9RORESERVED
REG SD HWDMA FREE8RWGCLKDIVCARD SD HWDMA Free run
have the same usage with GCLKDIVCARD CARD REG
REG HW DMA FREE7RWGCLKDIVCARD HW DMA Free run
have the same usage with GCLKDIVCARD CARD REG
REG HWDMA PAGE FREE6RWGCLKDIVCARD HWDMA PAGE Free run
have the same usage with GCLKDIVCARD CARD REG
REG DMA CTL FREE5RWGCLKDIVCARD DMA CTL Free run
have the same usage with GCLKDIVCARD CARD REG

REG DMA FIFO FREE

4

RW

GCLKDIVCARD DMA FIFO Free run
have the same usage with GCLKDIVCARD CARD REG

Reserved

3

RO

RESERVED

Reserved

2

RO

RESERVED

REG SD FREE

1

RW

GCLKDIVCARD SD Free run
have the same usage with GCLKDIVCARD CARD REG

REG SD CTL FREE

0

RW

GCLKDIVCARD SD CTL Free run
have the same usage with GCLKDIVCARD CARD REG

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED

SDRAM SECTOR 1 SIZE

15:0

RW

Length of Sector 1 in SDRAM

The actual size equals SECTOR 1 SIZE + 1, the unit is page(512 bytes)

Note: this sector register can only used in HW DMA mode,and when Ring Buffer disable.

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
SDRAM SECTOR 2 SIZE15:0RWLength of Sector 2 in SDRAM
The usage of this register is same as
SDRAM SECTOR 1 SIZE

...

Field Name

Bit

Access

Description

Reserved31:16RORESERVED
SDRAM SECTOR 3 SIZE15:0RWLength of Sector 3 in SDRAM
The usage of this register is same as
SDRAM SECTOR 1 SIZE

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
SDRAM SECTOR 4 SIZE15:0RWLength of Sector 4 in SDRAM
The usage of this register is same as
SDRAM SECTOR 1 SIZE

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
SDRAM SECTOR 5 SIZE15:0RWLength of Sector 5 in SDRAM
The usage of this register is same as
SDRAM SECTOR 1 SIZE

...

Field Name

Bit

Access

Description

Reserved31:16RORESERVED
SDRAM SECTOR 6 SIZE15:0RWLength of Sector 6 in SDRAM
The usage of this register is same as
SDRAM SECTOR 1 SIZE

...

Field Name

Bit

Access

Description

Reserved31:16RORESERVED
SDRAM SECTOR 7 SIZE15:0RWLength of Sector 7 in SDRAM
The usage of this register is same as
SDRAM SECTOR 1 SIZE

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Field Name

Bit

Access

Description

HW PAGE CNT31:16ROHW DMA Page Count
Indicate which page is being read or written, used in HW DMA mode.
Reserved15:5RORESERVED

HW BLOCK CNT

4:3

RO

HW DMA Block Counter for wait handshake signal from Flash Memory

SDRAM SECTOR CNT

2:0

RO

SDRAM Sector Count
Sector number that CARD CTL is Reading/Writing Cur- rently

...

Field Name

Bit

Access

Description

Reserved31:16RORESERVED
HW PAGE NUM0

15:0

RW

Declear Declare how many pages will be read or write start from the start page address of block0

The actual operation page number is (HW PAGE NUM0+1)

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
HW PAGE NUM115:0RWDeclear Declare how many pages will be read or write start from the start page address of block1
The actual page number is (HW PAGE NUM1 +1)

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
HW PAGE NUM215:0RWDeclear Declare how many pages will be read or write start from the start page address of block2
The actual page number is (HW PAGE NUM2 +1)

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
HW PAGE NUM315:0RWDeclear Declare how many pages will be read or write start from the start page address of block3
The actual page number is (HW PAGE NUM3 +1)

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Field Name

Bit

Access

Description

Reserved31:16RORESERVED
HW DELAY NUM

15:0

RW

HW Delay Number

Delay cyclesnumber cycles number in thehardware the hardware speedup DMA(HWDMA mode).



118.31 Debug signals for dma mode (dma debug)
Address: 0x9C003B7C
Reset: 0x0

這個 debug register 需要嗎 ?

Field Name

Bit

Access

Description

Reserved31:25RORESERVED
DMA SM24:22ROAXI bus state machine
0x0: Idle state(default)
0x1: Write command and address state
0x2: Read command and address state
0x3: Write Data state
0x4: Read Data state
outcnt21:11ROdata out counter
Account how many byte data has been transfer out to
SDRAM or device
incnt10:0ROdata in counter
Account how many byte data has been transfer into device
or SDRAM

...

Field Name

Bit

Access

Description

Reserved

31:8

RO

RESERVED

bootack

7:5

RO

Boot Ack Value
If bootmode enable,EMMC will send it's bootack value

boot mode

4

RUW

EMMC Have Boot Operation

fast boot

3

RW

Use Fast Boot Start Boot Operation
0x0:Use CMD0(0xFFFFFFFA) trigger boot opera- tion(default)
0x1: Use Pulldown CMD line trigger boot operation

boot data tmr

2

RW

Boot Data Timeout For 1s
0x0:0x3197500(52000000*(1/52MHz) =
1s)(52MHz)(default)
0x1: 0x18cba80(26000000*(1/26MHz) = 1s)(26MHz)

boot ack tmr

1

RW

Boot Ack Timeout For 50ms
0x0:0x27ac40(26000000*(1/52MHz) =
50ms)(52MHz)(default)
0x1: 0x13d620(13000000*(1/26MHz) = 50ms)(26MHz)

boot ack en

0

RW

Boot Ack In Boot Mode
0x0: Boot operation have not boot ack(default)
0x1: Boot operation have boot ack
This should set before excute boot operation.

...

Field Name

Bit

Access

Description

Reserved31:6RORESERVED

vol result

5:4

RO

HW Switch Voltage Sequence Result
0x0: Idle or In process(default)
0x1: Switch 1.8v voltage finished with no error
0x2: Switch 1.8v voltage finished with starting error
0x3: Switch 1.8v voltage timeout
These message is available when hw set vol enable.

hw set vol

3

RW

HW set Voltage to 1.8v
0:HW will not check 1.8v voltage switch se- quence(default)
1: HW will auto check 1.8v voltage switch sequence

sw set vol

2

RW

Software set Voltage to 1.8v
0: SW will set voltage 1.8v disable to CARD 1V8 di- rectly(default)
1: SW will set voltage 1.8v enable to CARD 1V8 directly

vol tmr

1:0

RW

Timeout for 1ms(hw set vol)
0x0: 100(100*(1/100khz) = 1ms)
0x1: 200(200*(1/200khz) = 1ms)
0x2: 300(300*(1/300khz) = 1ms)
0x3: 400(400*(1/400khz) = 1ms)(default)
This should be set before voltage switch sequence for SD UHS-I

...

Field Name

Bit

Access

Description

Reserved31:12RORESERVED
hw dma cmp clr11WUWrite 1 to this bit clear HW DMA interrupt flag
HW DMA CMP10ROHW DAM Complete interrupt flag
hw dma cmp en9RWHW DMA Data Transfer Complete Interrupt Enable
0: Disable the HW DMA data transfer complete interrupt(default)
DETECT INT CLR8WUClear card detect interrupt

DETECT INT

7

RO

Card plug-in or pull-out interrupt

DETECT INT EN

6

RW

Card plug-in or pull-out interrupt enable

sdio int clr

5

WU

Clear SDIO interrupt register in SDIO host
this signal is main used for clearing sdio interrupt register in 4-bit & multi-Block gaps

sdio int

4

RO

SDIO interrupt from SDIO card

sdio int en

3

RW

Enable SDIO Interrupt
0: Disable SDIO card interrupt(default)
1: Enable SDIO card interrupt

sd cmp clr

2

WO

Clear SD cmp Interrupt
Write 1 to this bit will generate a clear signal for clearing sd cmp interrupt register

sd cmp

1

RO

SD Operation Complete Interrupt
Sd page num*datalen bytes Data Transfer Complete for data transfer mode;
Cmd Transfer Complete for only cmd transfer mode;
Cmd & Rsp Transfer Complete for cmd with rsp transfer mode;
Error or timeout, the sources refer to bit[11:6] of sdstatus register;
Operation suspended(for SDIO Read Wait or Suspend flow)

sdcmpen

0

RW

Enable SD Interrupt
0: Disable SD interrupt(default)
1: Enable SD interrupt

...

Field Name

Bit

Access

Description

Reserved31:16RORESERVED
sd page num15:0RUWThe total Tx/Rx page number in the cmd(only for normal
DMA and PIO mode).
When config, it indicate how many pages will be read or write. The actual operation page number is ( PAGE NUM+ 1 )
When read, it indicate which page is being read or written, from page*(PAGE NUM) to page*0
default is '0'

...

Field Name

Bit

Access

Description

Reserved31:7RORESERVED

INT MULTI TRIG

6

RW

SDIO Interrupt Trigger Multiple time

0:When SDIO device send interrupt to controller,every interrupt only send one time(default)
1:When SDIO device send interrupt to controller,every interrupt may send multiple time when device interrupt remain low level multiple clock

SUS DATA FLAG

5

WO

Write 1 to Suspend SD state machine
When SW set this bit to suspend SD state machine, and then can select SUS, CON SD state machine

CON REQ

4

WO

write 1 to trigger SD state machine continue, and SDIO
host will be ready to continue data transfer
(PIO/normal DMA)If want to continue data transfer and not end SD state machine, so SW can config this bit and also continue interrupt period generation

SUS REQ

3

WO

write 1 to trigger SD state machine end
if want to suspend request, it needs SW to end SD state machine and then send suspend request.

RESU

2

WO

write 1 to trigger SD state machine to restore and also resume SDIO interrupt period generation rightly
those resume information(such as page cnt,addr..) is pro- vided by SW

S4MI

1

RW

trigger interrupt period generation between 4-bit read blocks
If card support interrupt between blocks of data in 4-bit SD mode, set this bit to generate interrupt period in block read gaps, default is '0'

RWC

0

RW

Read Wait Control signal
0: clear read wait(default)
1: write 1 will acknowledge SDIO host be ready to enter read wait control
SW set the RWC to hold transaction between the data blocks

...

Field Name

Bit

Access

Description

Reserved

31:3

RO

RESERVED

sdiorst

2

WO

SDIO Controller Interrupt Register Reset
High active, include sdio interrupt function

sdcrcrst

1

WO

SD Controller CRC Reset
High active, include CRC7 and CRC16 calculation

sdrst

0

WO

SD Controller Software Reset
High active
Note: The sdrst will only reset sd function which relates to device, but not reset register file of SD controller

...

Field Name

Bit

Access

Description

Reserved31:4RORESERVED
emmcctrl3WOStart Boot Operation Trigger Signal
Writting 1 to this bit will generate trigger signal for start boot operation (emmc use only)
sdioctrl2WODummy clock Trigger Signal
Writting 1 to this bit will generate trigger signal for trans- mitting dummy clock in IDLE state (sdio use only)
sdctrl[1]1WODummy clock Trigger Signal
Writting 1 to this bit will generate trigger signal for trans- mitting dummy clock
The dummy cycle number config in sd tx dummy num register
sdctrl[0]0WONew Command Trigger Signal
Writting 1 to this bit will generate trigger signal for starting transaction

...

Field Name

Bit

Access

Description

Reserved31:19RORESERVED
sdstatus18:0ROSD Controller Status
bit0 : Dummy ready
bit1 : Response buffer full, high active
bit2 : Transmitted data buffer empty, high active bit3 : Receive data buffer full, high active
bit4 : Status of pin cmd
bit5 : Status of pin SD data0
bit6 : Timeout flag of waiting response, high active
bit7 : Timeout flag of waiting card's CRC check result, high active
bit8 : Wait STB(start bit) timeout, when read data from card
bit9 : Rsp crc7 error
bit10: CRC Token Check error
bit11: Rdata CRC16 error(all CRC16)
bit12: Suspend state ready bit13: Busy cycle
bit14: Status of pin SD data1 bit15: Status of SD SENSE
bit16: Timeout flag of waiting boot ack, high active bit17: Timeout flag of waiting boot data, high active
bit18: EMMC boot ack error, high active

...

Field Name

Bit

Access

Description

Reserved31:15RORESERVED
sdstate new14:8RONew SD state machine of SD Controller
bit14 : 0: Transaction have no finish or idle
1: Transaction finish or idle(default)
bit13 : 0: Transaction have no error or timeout(default)
1: Transaction error or timeout
bit12:8 : represent the state machine other states,don't care
Reserved7RORESERVED
sdcrdcrc6:4ROThe CRC Token Check Result
0x0 : reserved(default)
0x2 : CRC check correct
0x5 : CRC check incorrect others: reserved
Reserved3RORESERVED
sdstate2:0ROState Machine of SD Controller
0x0 : Idle(default)
0x1 : Transmit Dummy Clock
0x2 : Transmit SD Command
0x3 : Receiveing SD Response
0x4 : Transmitting Data
0x5 : Receiving CRC Token
0x6 : Receiving Data
0x7 : reserved

...

Field Name

Bit

Access

Description

Reserved31:10RORESERVED
HWSD SM

9:0

RO

The Hardware SD State

bit6: SD HW DMA Error

bit7: SD HW DMA Done

Note: when this register equals '0', it means sd controller in idle state.

...

Field Name

Bit

Access

Description

Reserved31:11RORESERVED
sd data len

10:0

RW

Data Length of One Block

The actual length equals (sddatalen + 1)

0x0 : 1 byte

0x1 : 2 byte

...

0x1ff : 512 byte(default)

...

0x7ff : 2048 byte

...

Field Name

Bit

Access

Description

Reserved31:11RORESERVED
sd rd dly sel10:8RWSelection Signal of SD Read Delay
Delay the time that SD controller sample rsp and data from sd interface, the unit is 1*DPLL
0x0: no delay(default)
0x1: delay 1*DPLL clock
0x2: delay 2*DPLL clock
0x3: delay 3*DPLL clock
0x4: delay 4*DPLL clock
0x5: delay 5*DPLL clock
0x6: delay 6*DPLL clock
0x7: delay 7*DPLL clock
Reserved7RORESERVED
sd wr dly sel6:4RWSelecting Signal of SD Write Delay
Delay SD tx cmd/data to card, the unit is 1*DPLL
0x0: no delay(default)
0x1: delay 1*DPLL clock
0x2: delay 2*DPLL clock
0x3: delay 3*DPLL clock
0x4: delay 4*DPLL clock
0x5: delay 5*DPLL clock
0x6: delay 6*DPLL clock
0x7: delay 7*DPLL clock
Reserved3RORESERVED
sd clk dly sel2:0RW

Selecting Signal of SD Clock Delay

Delay SD clock to card, the unit is 1*DPLL

0x0: no delay(default)

0x1: delay 1*DPLL clock

0x2: delay 2*DPLL clock

0x3: delay 3*DPLL clock

0x4: delay 4*DPLL clock

0x5: delay 5*DPLL clock

0x6: delay 6*DPLL clock

0x7: delay 7*DPLL clock

...

Field Name

Bit

Access

Description

Reserved31:29RORESERVED
sd rx dat tmr28:0RWmax timer value selection
default value 29'h01321d00

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