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| Field Name | Bit | Access | Description |
| Reserved | 31:8 | RO | RESERVED |
| J HS TX DELAY | 7:6 | RW | Fine tune TX Delay 0x0 : No delay(default). 0x1 : Delay 1 clock. 0x2 : Delay 2 clock. 0x3 : No delay. |
| J HS TX PWRSAV | 5 | RW | High Speed TX power saving. When this item actives, it means TX driver will turn on with TXValid. When this item is low, it means TX driver will always turn on. |
| J HS RX DROP2 | 4 | RW | 缺 Register Full Description ?Set the EOP receive condition sensitive If DEV_DET fall very quickly, this may cause some valid EOP bit lose and cause correct packet become RXERROR, so this register set medium EOP detection. 0x0: do nothing(default) |
| J HS RX DROP4 | 3 | RW缺 Register Full Description ? | Set the EOP receive condition very sensitive If DEV_DET fall very quickly, this may cause some valid EOP bit lose and cause correct packet become RXERROR, so this register set very sensitive EOP detection. 0: do nothing(default) |
| J HS RX LPFIL | 2:1 | RW | CDR bandwidth selection這裡要敘述不一樣的值如何 select bandwidth data channel phase shift precision 0x0: shift precision is very high 0x1: shift precision is high 0x2: shift precision is medium 0x3: shift precision is slow |
| J FS TX PREDR IDLE | 0 | RW | For 1st cross over point perfection 0: Disable(default) 1 : Enable |
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| Field Name | Bit | Access | Description |
| Reserved | 31:8 | RO | RESERVED |
| J DPN | 7:4 | RW | DP Full speed falling time select. The larger the value, the shorter the DP falling transition time. Default: 4'b0000 這裡要敘述不一樣的值如何 select |
| J DPP | 3:0 | RW | DP Full speed rising time select. The larger the value, the shorter the DP rising transition time. Default: 4'b0000這裡要敘述不一樣的值如何 select |
149.3 CONFIG3 (cfg3)
Address: 0x9C004A8C
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Field Name | Bit | Access | Description |
Reserved | 31:8 | RO | RESERVED |
SUCC CNTR | 7:4 | RU | Success Bit mode success counter這裡要敘述什麼的 success counter When successive 15 packages success, BIST test success and done. |
FAIL CNTR | 3:0 | RU | Fail Bit mode fail counter這裡要敘述什麼的 fail counter When successive 15 packages fail, BIST test fail and done. |
149.6CONFIG66 CONFIG6 (cfg6)
Address: 0x9C004A98
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| Field Name | Bit | Access | Description |
| Reserved | 31:8 | RO | RESERVED |
| J DMN | 7:4 | RW | DM Full speed falling time select.需要詳細 description. The larger the value, the shorter the DP falling transition time. Default: 4'b0000 |
| J DMP | 3:0 | RW | DM Full speed rising time select.需要詳細 description. The larger the value, the shorter the DP rising transition time. Default: 4'b0000 |
149.7 CONFIG7 (cfg7)
Address: 0x9C004A9C
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| Field Name | Bit | Access | Description | ||
| Reserved | 31:8 | RO | RESERVED | ||
J FORCE DISCHRGVBUSReserved | 7 | RW | Force VBUS discharge for FT. 這是 FT 才要用嗎 ? 如果是可以移除 | J FORCE CHRGVBUS | RESERVED |
Reserved | 6 | RW | Force VBUS charge for FT. 這是 FT 才要用嗎 ? 如果是可以移除RESERVED | ||
NA | 5:0 | RW | NA | ||
J AC2 0 B | 5:3 | RW | OTG Discharge Current Option. 其他值也要說明. | ||
J AC2 0 | 2:0 | RW | OTG Charge Current Option. 其他值也要說明. |
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