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Address | Group No. | Register Name | Description | |
|---|---|---|---|---|
0x9C002880 | G81.0 | icm0_cfg0 | ICM0 Config Register 0 | |
0x9C002884 | G81.1 | icm0_cfg1 | ICM0 Config Register 1 | |
0x9C002888 | G81.2 | icm0_cfg2 | ICM0 Internal Counter Scaler | |
0x9C00288C | G81.3 | icm0_cfg3 | ICM0 Test Signal Scalerreserved | reserved |
0x9C002890 | G81.4 | icm0_cnt | ICM0 Interrupt Trigger Counter Value | |
0x9C002894 | G81.5 | icm0_pulse_width_h | ICM0 Pulse Width H | |
0x9C002898 | G81.6 | icm0_pulse_width_l | ICM0 Pulse Width L | |
0x9C00289C | G81.7 | icm1_cfg0 | ICM1 Config Register 0 | |
0x9C0028A0 | G81.8 | icm1_cfg1 | ICM1 Config Register 1 | |
0x9C0028A4 | G81.9 | icm1_cfg2 | ICM1 Internal Counter Scaler | |
0x9C0028A8 | G81.10 | icm1_cfg3 | ICM1 Test Signal Scalerreserved | reserved |
0x9C0028AC | G81.11 | icm1_cnt | ICM1 Interrupt Trigger Counter Value | |
0x9C0028B0 | G81.12 | icm1_pulse_witdh_h | ICM1 Pulse Width H | |
0x9C0028B4 | G81.13 | icm1_pulse_width_l | ICM1 Pulse Width L | |
0x9C0028B8 | G81.14 | icm2_cfg0 | ICM2 Config Register 0 | |
0x9C0028BC | G81.15 | icm2_cfg1 | ICM2 Config Register 1 | |
0x9C0028C0 | G81.16 | icm2_cfg2 | ICM2 Internal Counter Scaler | |
0x9C0028C4 | G81.17 | icm2_cfg3 | ICM2 Test Signal Scalerreserved | reserved |
0x9C0028C8 | G81.18 | icm2_cnt | ICM2 Interrupt Trigger Counter Value | |
0x9C0028CC | G81.19 | icm2_pulse_witdh_h | ICM2 Pulse Width H | |
0x9C0028D0 | G81.20 | icm2_pulse_width_l | ICM2 Pulse Width L | |
0x9C0028D4 | G81.21 | icm3_cfg0 | ICM3 Config Register 0 | |
0x9C0028D8 | G81.22 | icm3_cfg1 | ICM3 Config Register 1 | |
0x9C0028DC | G81.23 | icm3_cfg2 | ICM3 Internal Counter Scaler | |
0x9C0028E0 | G81.24 | icm3_cfg3 | ICM3 Test Signal Scalerreserved | reserved |
0x9C0028E4 | G81.25 | icm3_cnt | ICM3 Interrupt Trigger Counter Value | |
0x9C0028E8 | G81.26 | icm3_pulse_witdh_h | ICM3 Pulse Width H | |
0x9C0028EC | G81.27 | icm3_pulse_width_l | ICM3 Pulse Width L | |
0x9C0028F0 | G81.28 | reserved | reserved | |
0x9C0028F4 | G81.29 | reserved | reserved | |
0x9C0028F8 | G81.30 | reserved | reserved | |
0x9C0028FC | G81.31 | reserved | reserved |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm0 clk sel | 8:6 | RW | ICM0 Clock Source Select (Default value 是哪一個 ? 麻煩在後方註明 (Default)) |
| icm0 mux sel | 5:3 | RW | Select input signal source. |
| icm0 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm0 en | 0 | RW | ICM0 enable When set this bit to 0, it mean disabled input capture module 0 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| icm0 cnt scale | 31:0 | RW | ICM0 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.3 ICM0 Test Signal Scaler (icm0 cfg3) Reserve
Address: 0x9C00288C
Reset: 0x0000 0000
| Field Name | Bit | Access | Description | |
| icm0 test sig scalereserve | 31:0 | RW | reserve | ICM0 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk) |
81.4 ICM0 Interrupt Trigger Counter Value (icm0 cnt81.4 ICM0 Interrupt Trigger Counter Value (icm0 cnt)
Address: 0x9C002890
Reset: 0x0000 0000
...
| Field Name | Bit | Access | Description |
| icm1 cnt scale | 31:0 | RW | ICM1 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.10 ICM1 Test Signal Scaler (icm1 cfg3) Reserve
Address: 0x9C0028A8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 test sig scalereserve | 31:0 | RW | ICM1 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk)reserve |
81.11 ICM1 Interrupt Trigger Counter Value (icm1 cnt)
Address: 0x9C0028AC
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm2 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm2 mux sel | 5:3 | RW | Selec input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0Others: 0 |
| icm2 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm2 en | 0 | RW | ICM2 enable When set this bit to 0, it mean disabled input capture module 2 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| icm2 cnt scale | 31:0 | RW | ICM2 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.17 ICM2 Test Signal Scaler (icm2 cfg3) Reserve
Address: 0x9C0028C4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 test sig scalereserve | 31:0 | RW | ICM2 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk) |
...
reserve |
81.18 ICM2 Interrupt Trigger Counter Value (icm2 cnt)
Address: 0x9C0028C8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 cnt | 31:0 | RO | ICM2 Interrupt Trigger Counter Value Record the internal counter value when interrupt happened. Interrupt trigger mode can be select by register G81.1 bit1~0. |
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm3 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 0 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm3 mux sel | 5:3 | RW | Select input signal source. 0: Input 0 1: Input 1 2: Input 2 3: Input 3 4: Test Signal Others: 0 |
| icm3 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm3 en | 0 | RW | ICM3 enable When set this bit to 0, it mean disabled input capture module 3 and the interrupt also cleared. |
...
| Field Name | Bit | Access | Description |
| icm3 cnt scale | 31:0 | RW | ICM3 Internal Counter Scaler Clock prescaler 0-(2ˆ32-1). clk cnt = ext clk / (icmx cnt scale+1) |
81.24 ICM3 Test Signal Scaler (icm3 cfg3) Reserve
Address: 0x9C0028E0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm3 test sig scalereserve | 31:0 | RW | ICM3 Test Signal Scaler Test signal prescaler 0-(2ˆ32-1). clk test = sysclk / (icmx test sig scale+1) On clk test rising edge, system will generate 1T pulse signal. The Test Signal Period = (icm0 test sig scale+1) + 1, UNIT : T(sysclk)reserve |
81.25 ICM3 Interrupt Trigger Counter Value (icm3 cnt)
Address: 0x9C0028E4
Reset: 0x0000 0000
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