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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm0 clk sel | 8:6 | RW | ICM0 Clock Source Select (Default value 是哪一個 ? 麻煩在後方註明 (Default)) |
| icm0 mux sel | 5:3 | RW | Select input signal source. |
| icm0 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm0 en | 0 | RW | ICM0 enable When set this bit to 0, it mean disabled input capture module 0 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| icm0 pulse width h | 31:0 | RO | ICM0 Pulse Width H Square pulse high level width (unit : t ext , icm0_clk) |
81.6 ICM0 Pulse Width L (icm0 pulse width l)
Address: 0x9C002898
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm0 pulse width l | 31:0 | RO | ICM0 Pulse Width L Square pulse low level width (unit : t ext , icm0_clk) |
81.7 ICM1 Config Register 0 (icm1 cfg0)
Address: 0x9C00289C
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| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm1 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 00 (default) 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm1 mux sel | 5:3 | RW | Select input signal source. 0: Input 00 (default) 1: Input 1 2: Input 2 3: Input 3 Others: 0 |
| icm1 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm1 en | 0 | RW | ICM1 enable When set this bit to 0, it mean disabled input capture module 1 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| icm1 pulse width h | 31:0 | RO | ICM1 Pulse Width H Square PWM pulse high level width (unit : t ext , icm1_clk) |
81.13 ICM1 Pulse Width L (icm1 pulse width l)
Address: 0x9C0028B4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm1 pulse width l | 31:0 | RO | ICM1 Pulse Width L Square PWM pulse low level width (unit : t ext , icm1_clk) |
81.14 ICM2 Config Register 0 (icm2 cfg0)
Address: 0x9C0028B8
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm2 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 00 (default) 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm2 mux sel | 5:3 | RW | Selec input signal source. 0: Input 00 (default) 1: Input 1 2: Input 2 3: Input 3 Others: 0 |
| icm2 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm2 en | 0 | RW | ICM2 enable When set this bit to 0, it mean disabled input capture module 2 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| icm2 pulse width h | 31:0 | RO | ICM2 Pulse Width H Square PWM pulse high level width (unit : t ext , icm2_clk) |
81.20 ICM2 Pulse Width L (icm2 pulse width l)
Address: 0x9C0028D0
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| icm2 pulse width l | 31:0 | RO | ICM2 Pulse Width L Square PWM pulse low level width (unit : t ext , icm2_clk) |
81.21 ICM3 Config Register 0 (icm3 cfg0)
Address: 0x9C0028D4
Reset: 0x0000 0000
| Field Name | Bit | Access | Description |
| Write Mask Bits | 31:16 | RW | Write Mask Bits Corresponding Mask Bits for Bit[15:0] Example: If user want to set bit0 = 1, than he should set bit16 to 1 (0x 0001) to enable bit0 functionality |
| Reserve | 15:9 | RO | RESERVED |
| icm3 clk sel | 8:6 | RW | Select clock source. (External CLK range 32K-210M Hz) 0: External CLK 00 (default) 1: External CLK 1 2: External CLK 2 3: External CLK 3 4: SYSCLK 5: 27 MHz 6: 32 KHz Others : 0 |
| icm3 mux sel | 5:3 | RW | Select input signal source. 0: Input 00 (default) 1: Input 1 2: Input 2 3: Input 3 Others: 0 |
| icm3 int clr | 2 | W1C | Clear the interrupt. Write 1 to clear interrupt, HW will recover this bit to 0 automatically. |
| Reserve | 1 | RW | RESERVED |
| icm3 en | 0 | RW | ICM3 enable When set this bit to 0, it mean disabled input capture module 3 and the interrupt also cleared. |
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| Field Name | Bit | Access | Description |
| icm3 pulse width h | 31:0 | RO | ICM3 Pulse Width H Square PWM pulse high level width (unit : t ext , icm3_clk) |
81.27 ICM3 Pulse Width L (icm3 pulse width l)
Address: 0x9C0028EC
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Field Name | Bit | Access | Description |
icm3 pulse width l | 31:0 | RO | ICM3 Pulse Width L Square PWM pulse low level width (unit : t ext , icm3_clk) |
81.28 (Reserved)
Address: 0x9C0028F0
Reset: 0x0000 0000
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