7.1 Introduction
The Real Time Clock (RTC) is a feature that can keep counting the time using external back-up battery when main system power-off. In this design a 32-bits counter is implemented for second counting. The conversion from second to time and date is calculated by software.
This design also provides an alarm feature that can be used to allow main system to 'wake up' after shut down to execute tasks in a certain moment. The alarm setting in seconds, the conversion from time and date to second is calculated by software.
Back-up power source can used a Super Cap or a coin battery (like CR2032), and build-in charging circuit without any external component.
The control registers locate at RGST Table Group116 registers which memory map address are 0x9C003A00~0x9C003A7F. The SP7021 RTC function include below features.
- Sustain more than one year with 250ma-H battery.
- RTC with alarm timer module has its own interrupt signal internally .
- Backup power failure flag (Group116.16 bit13~12 bat cmp hytbit9 bat_pg_o & bit8 supply_PG_o) to indicate the RTC information is not reliable when V-battery is lower than safe voltage. User can read this the flag to monitor battery status.
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| Field Name | Bit | Access | Description |
| Bit Write Mask | 31:16 | RW | |
| Reserved | 15:14 | RO | |
| bat cmp hyt | 13:12 | RW | The hysteresis window select of comparator which is used to detect VBAT State what is the effect if the result is higher (or lower) than the threshold selectedis greater than 1.9V 2'b00: 11mV (default) |
| supply cmp hyt | 11:10 | RW | The hysteresis window select of comparator which is used to detect AVDD33 AVDD33 is greater than 2.2V 2'b00: 11mV (default) |
| bat_pg_o | 9 | RO | Detect VBAT is greater than 1.9V 0: VBAT <1.9V |
| supply_pg_o | 8 | RO | Detect AVDD33 is greater than 2.2V 0: AVDD33<2.2V |
| Reserved | 7:6 | RO | |
| timer_freeze | 5 | RW | Timer Freeze 0: none (default) |
| DIS_SYS_RST_RTC | 4 | RW | Disable System Reset RTC 0: enable (default) |
| rtc32k_mode_reset | 3 | RW | Reset rtc32k (analog) For reset signal, state active high or low. Need S/W to program from high to low to de-assert reset or not. Briefly describe what happen after reset) 0: The counter of RTC32K will go on (default) 1: Reset the counter of RTC32K After reset,read G116.17(rtc timer out) value, check reset or not |
| alarm_en_overdue | 2 | RW | Enable Alarm (current time > alarm time) 0: disable (default) |
alarm_en_pmc | 1 | RW | Enable Alarm for PMC 0: disable (default) 1: enable |
| alarm_en | 0 | RW | Enable Alarm for system 0: disable (default) 1: enable |
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116.22 Get Reset Records (rtc reset record)
Address: 0x9C003A58
Reset: 0x0000 0000
HW will update "reset_record" bits before reset , so user can check this item to know the reset reason.
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