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Field Name | Bit | Access | Description |
SIZE | 31:16 | RW | DMA Transfer Length |
Reserved | 15:1 | RO | RESERVED |
EN | 0 | RU | DMA enable Enable It will be auto-clear to 0 when DMA finished |
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Field Name | Bit | Access | Description |
| CNT M | 31:24 | RW | Counter increment part Increment Part |
| NK | 23:16 | RW | Key length Length Only support 4,6,8 |
| Reserved | 15:8 | RO | RESERVED |
| ENDEC | 7 | RW | En/Decrypt 1: decrypt |
| MODE | 6:0 | RW | MODE 0x1: ECB 0x2: CBC Others: Reserved |
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Field Name | Bit | Access | Description |
| IPTR | 31:0 | RW | IV/ICB pointer Pointer |
84.5 AES Dma Parameter 2 (AESPAR2)
Address: 0x9C002A14
Reset: 0x0
Field Name | Bit | Access | Description |
| KPTR | 31:0 | RW | Key pointer Pointer |
84.6 HASH DMA Control Status register (HASHDMACS)
Address: 0x9C002A18
Reset: 0x0
Field Name | Bit | Access | Description |
SIZE | 31:16 | RW | DMA Transfer Length |
Reserved | 15:1 | RO | RESERVED |
EN | 0 | RU | DMA enable Enable It will be auto-clear to 0 when DMA finished |
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Field Name | Bit | Access | Description |
| SPTR | 31:0 | RW | Source address Address must be 32B aligned |
84.8 HASH Destination Data pointer (HASHDPTR)
Address: 0x9C002A20
Reset: 0x0
Field Name | Bit | Access | Description |
| DPTR | 31:0 | RW | Destination address Address must be 32B aligned |
84.9 HASH Dma Parameter 0 (HASHPAR0)
Address: 0x9C002A24
Reset: 0x0
Field Name | Bit | Access | Description |
| Reserved | 31:18 | RO | RESERVED |
D | 17:16 | RW | output hash length Output Hash Length |
Reserved | 15:7 | RO | RESERVED |
MODE | 6:0 | RW | MODE 0x1: SHA3 0x2: GHASH Others:reserved |
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Field Name | Bit | Access | Description |
| HPTR | 31:0 | RW | Subkey pointer Pointer GHASH only |
84.12 RSA DMA Control Status register (RSADMACS)
Address: 0x9C002A30
Reset: 0x0
Field Name | Bit | Access | Description |
| SIZE | 31:16 | RW | DMA Transfer Length |
Reserved | 15:1 | RO | RESERVED |
EN | 0 | RU | DMA enable Enable It will be auto-clear to 0 when DMA finished |
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Field Name | Bit | Access | Description |
| SPTR | 31:0 | RW | Source(X) address Address Z=X**Y (mod N),must be 32B aligned |
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Field Name | Bit | Access | Description |
| DPTR | 31:0 | RW | Destination(Z) address Address Z=X**Y (mod N),must be 32B aligned |
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Field Name | Bit | Access | Description |
| D | 31:16 | RW | N length Length Only support 64*n(1¡=n¡=32) |
| Reserved | 15:8 | RO | RESERVED |
| PRECALC | 7 | RW | Precalculate P2 0: Precalculate and write back to pointer from P2PTR 1: Fetch from P2PTR |
| Reserved | 6:0 | RO | RESERVED |
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Field Name | Bit | Access | Description |
| YPTR | 31:0 | RW | Y pointer Pointer Z=X**Y (mod N) |
84.17 RSA Dma Parameter 2 (RSAPAR2)
Address: 0x9C002A44
Reset: 0x0
Field Name | Bit | Access | Description |
| NPTR | 31:0 | RW | N pointer Pointer Z=X**Y (mod N) |
84.18 RSA Dma Parameter 3 (RSAPAR3)
Address: 0x9C002A48
Reset: 0x0
Field Name | Bit | Access | Description |
| P2PTR | 31:0 | RW | P2 pointerP2 Pointer P2 = P**2(mod N) |
84.19 RSA Dma Parameter 4 (RSAPAR4)
Address: 0x9C002A4C
Reset: 0x0
Field Name | Bit | Access | Description |
| WPTR | 31:0 | RW | W low dword Low Dword W = -N**-1(mod N) |
84.20 RSA Dma Parameter 5 (RSAPAR5)
Address: 0x9C002A50
Reset: 0x0
Field Name | Bit | Access | Description |
| WPTR | 31:0 | RW | W high dwordHigh Dword W = -N**-1(mod N) |
84.21 AES DMA Command Ring Control Register (AESDMA CRCR)
Address: 0x9C002A54
Reset: 0x0
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Field Name | Bit | Access | Description |
EN | 31 | RW | Auto DMA enable Enable |
ERF | 30 | W1C | Event ring Ring Full |
Reserved | 29:16 | RO | RESERVED |
Size | 15:0 | RW | Event Ring Size |
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Field Name | Bit | Access | Description |
EN | 31 | RW | Auto DMA enable Enable |
ERF | 30 | W1C | Event ring Ring Full |
Reserved | 29:16 | RO | RESERVED |
Size | 15:0 | RW | Event Ring Size |
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Field Name | Bit | Access | Description |
| VERSION | 31:0 | ROthe | date of versionThe Date of Version |
85.1Interrupt Enable (SECIE)
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