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前面章节的七段数码管显示控制器IP核设计是AMBA APB总线接口，而我们FBIO Wrapper是AMBA AXI总线接口, 不能直接连接在一起，需要一个AXI2ABP 的Bridge进行连接，如下

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本实验提供了相应的AXI2ABP Bridge基础文件axi2apb_64.v，如下

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The seven-segment digital display controller IP core design in the previous chapter is the AMBA APB bus interface, We choose apb_ bus_ m32_bridge module from Bus Bridge series ,so the APB master bus interface provided by the bus bride module is used to connect our IP as follows

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This experiment provides the corresponding Bus Bridge module file: apb_bus_m32_bridge.v and apb_bus_m32_bridge.edf

The corresponding connection between the design case and the hardware platform (SP7021 motherboard and FPGA daughter board) pin is shown in the following table: 1: U20B on the motherboard is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the motherboard and the FPGA

Image Added

Design Demo	FPGA daughter board			SP7021 main (mother) board
led_7segment_ctl	J2		U1E	U20B
Top Port Name	Schematic Name		FPGA I/O	Schematic Name
	1	GND		51	GND
	2	GND		52	GND
FPGA_PAD[0]	3	B34_L24_N	T8	53	FBIO_PAD_0
FPGA_PAD[43]	4	B34_L24_P	R8	54	FBIO_PAD_1
	5	VIN		55	VCC(3.3V)
	6	VCCIO34		56	VCC(3.3V)
FPGA_PAD[1]	7	B34_L21_N	V9	57	FBIO_PAD_2
FPGA_PAD[42]	8	B34_L21_P	U9	58	FBIO_PAD_3
FPGA_PAD[2]	9	B34_L18_N	N6	59	FBIO_PAD_4
FPGA_PAD[41]	10	B34_L18_P	M6	60	FBIO_PAD_5
FPGA_PAD[3]	11	B34_L22_N	U6	61	FBIO_PAD_6
FPGA_PAD[40]	12	B34_L22_P	U7	62	FBIO_PAD_7
FPGA_PAD[4]	13	B34_L20_N	V6	63	FBIO_PAD_8
FPGA_PAD[39]	14	B34_L20_P	V7	64	FBIO_PAD_9
FPGA_PAD[5]	15	B34_L23_N	T6	65	FBIO_PAD_10
FPGA_PAD[38]	16	B34_L23_P	R7	66	FBIO_PAD_11
FPGA_PAD[6]	17	B34_L10_N	V4	67	FBIO_PAD_12
FPGA_PAD[37]	18	B34_L10_P	V5	68	FBIO_PAD_13
FPGA_PAD[7]	19	B34_L19_P	R6	69	FBIO_PAD_14
FPGA_PAD[36]	20	B34_L19_N	R5	70	FBIO_PAD_15
FPGA_PAD[8]	21	B34_L8_P	U4	71	FBIO_PAD_16
FPGA_PAD[35]	22	B34_L8_N	U3	72	FBIO_TCLK
FPGA_PAD[9]	23	B34_L9_N	V2	73	FBIO_RCLK
FPGA_PAD[34]	24	B34_L9_P	U2	74	FBIO_PAD_17
FPGA_PAD[10]	25	B34_L7_N	V1	75	FBIO_PAD_18
FPGA_PAD[33]	26	B34_L7_P	U1	76	FBIO_PAD_19
FPGA_PAD[11]	27	B34_L13_P	N5	77	FBIO_PAD_20
FPGA_PAD[32]	28	B34_L13_N	P5	78	FBIO_PAD_21
FPGA_PAD[12]	29	B34_L12_P	T5	79	FBIO_PAD_22
FPGA_PAD[31]	30	B34_L12_N	T4	80	FBIO_PAD_23
FPGA_PAD[13]	31	B34_L11_N	T3	81	FBIO_PAD_24
FPGA_PAD[30]	32	B34_L11_P	R3	82	FBIO_PAD_25
FPGA_PAD[29]	33	B34_L14_P	P4	83	FBIO_PAD_26
FPGA_PAD[28]	34	B34_L14_N	P3	84	FBIO_PAD_27
FPGA_PAD[14]	35	B34_L16_N	N4	85	FBIO_PAD_28
FPGA_PAD[27]	36	B34_L16_P	M4	86	FBIO_PAD_29
FPGA_PAD[15]	37	B34_L17_N	T1	87	FBIO_PAD_30
FPGA_PAD[26]	38	B34_L17_P	R1	88	FBIO_PAD_31
FPGA_PAD[16]	39	B34_L15_N	R2	89	FBIO_PAD_32
FPGA_PAD[25]	40	B34_L15_P	P2	90	FBIO_PAD_33
FPGA_PAD[17]	41	B34_L3_N	N1	91	FBIO_PAD_34
FPGA_PAD[24]	42	B34_L3_P	N2	92	FBIO_PAD_35
FPGA_PAD[18]	43	B34_L1_N	M1	93	FBIO_PAD_RSTB
FPGA_PAD[23]	44	B34_L1_P	L1	94	EXT0_INT
	45	VCCIO34		95	VCC(3.3V)
	46	VIN		96	VCC(3.3V)
FPGA_PAD[19]	47	B34_L4_P	M3	97	EXT1_INT
FPGA_PAD[20]	48	B34_L4_N	M2	98
	49	GND		99	GND
	50	GND		100	GND

2: U20A on the main board is connected to J1 of the FPGA daughter board (Pin pins correspond to one, such as 1-1 ...), and the 42 pin IO (3.3v) of FPGA Bank 35 is extended via J17 for users; Connect J2 of the test expansion board (Pin pin corresponds to one, such as 1-1 ...), provide FPGA IO expansion

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Design Demo	FPGA daughter board			SP7021 main board				Extended test daughter board
led_7segment_ctl	J1		U1F	U20A		J17		J2
Top Port Name	Schematic Name		FPGA I/O	Schematic Name		Schematic Name		Schematic Name
	1	GND		1	GND	3	GND	3	GND
	2	GND		2	GND	4	GND	4	GND
	3	B35_L23_N	K1	3	B35_L23_N	5	B35_L23_N	5	PMOD8
	4	B35_L23_P	K2	4	B35_L23_P	6	B35_L23_P	6	PMOD7
	5	VIN		5	VIN	1	VCC	1	VCC
	6	VCCIO35		6	VCCIO35	2	VCC	2	VCC
	7	B35_L15_N	G2	7	B35_L15_N	7	B35_L15_N	7	PMOD6
	8	B35_L15_P	H2	8	B35_L15_P	8	B35_L15_P	8	PMOD5
	9	B35_L13_N	F3	9	B35_L13_N	9	B35_L13_N	9	PMOD4
	10	B35_L13_P	F4	10	B35_L13_P	10	B35_L13_P	10	PMOD3
	11	B35_L12_N	D3	11	B35_L12_N	11	B35_L12_N	11	PMOD1
	12	B35_L12_P	E3	12	B35_L12_P	12	B35_L12_P	12	LED_D1
	13	B35_L22_P	J3	13	B35_L22_P	13	B35_L22_P	13	LED_D2
	14	B35_L22_N	J2	14	B35_L22_N	14	B35_L22_N	14	PMOD2
	15	B35_L17_N	G1	15	B35_L17_N	15	B35_L17_N	15	LED_D3
	16	B35_L17_P	H1	16	B35_L17_P	16	B35_L17_P	16	LED_D4
	17	B35_L18_N	E1	17	B35_L18_N	17	B35_L18_N	17	LED_D5
	18	B35_L18_P	F1	18	B35_L18_P	18	B35_L18_P	18	LED_D6
	19	B35_L14_N	D2	19	B35_L14_N	19	B35_L14_N	19	LED_D7
	20	B35_L14_P	E2	20	B35_L14_P	20	B35_L14_P	20	LED_D8
	21	B35_L16_P	C2	21	B35_L16_P	21	B35_L16_P	21	SPI_WP
	22	B35_L16_N	C1	22	B35_L16_N	22	B35_L16_N	22	SPI_DO
	23	B35_L9_N	A1	23	B35_L9_N	23	B35_L9_N	23	SPI_CS
	24	B35_L9_P	B1	24	B35_L9_P	24	B35_L9_P	24	SPI_HOLD
	25	B35_L10_P	B3	25	B35_L10_P	25	B35_L10_P	25	SPI_CLK
	26	B35_L10_N	B2	26	B35_L10_N	26	B35_L10_N	26	SPI_DI
FPGA_LED[8]	27	B35_L8_N	A3	27	B35_L8_N	27	B35_L8_N	27	U1-1
FPGA_LED[9]	28	B35_L8_P	A4	28	B35_L8_P	28	B35_L8_P	28	U2-1
FPGA_LED[10]	29	B35_L11_N	D4	29	B35_L11_N	29	B35_L11_N	29	U3-1
FPGA_LED[11]	30	B35_L11_P	D5	30	B35_L11_P	30	B35_L11_P	30	U4-1
FPGA_LED[1]	31	B35_L3_N	A5	31	B35_L3_N	31	B35_L3_N	31	LED-B
FPGA_LED[5]	32	B35_L3_P	A6	32	B35_L3_P	32	B35_L3_P	32	LED-F
FPGA_LED[0]	33	B35_L2_N	B6	33	B35_L2_N	33	B35_L2_N	33	LED-A
FPGA_LED[4]	34	B35_L2_P	B7	34	B35_L2_P	34	B35_L2_P	34	LED-E
FPGA_LED[3]	35	B35_L7_N	B4	35	B35_L7_N	35	B35_L7_N	35	LED-D
FPGA_LED[7]	36	B35_L7_P	C4	36	B35_L7_P	36	B35_L7_P	36	LED-RA
FPGA_LED[2]	37	B35_L1_N	C5	37	B35_L1_N	37	B35_L1_N	37	LED-C
FPGA_LED[6]	38	B35_L1_P	C6	38	B35_L1_P	38	B35_L1_P	38	LED-G
	39	B35_L5_N	E5	39	B35_L5_N	39	B35_L5_N	39	GND
	40	B35_L5_P	E6	40	B35_L5_P	40	B35_L5_P	40	GND
	41	B35_L6_N	D7	41	B35_L6_N	41	B35_L6_N
	42	B35_L6_P	E7	42	B35_L6_P	42	B35_L6_P
	43	B35_L19_P	G6	43	B35_L19_P	43	B35_L19_P
	44	B35_L19_N	F6	44	B35_L19_N	44	B35_L19_N
	45	VCCIO35		45	VCCIO35	49	VCC
	46	VIN		46	VIN	50	VCC
	47	B35_L4_N	C7	47	B35_L4_N	45	B35_L4_N
	48	B35_L4_P	D8	48	B35_L4_P	46	B35_L4_P
	49	GND		49	GND	47	GND
	50	GND		50	GND	48	GND

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