The seven-segment digital display controller IP core design in the previous chapter is the AMBA APB bus interface, and our FBIO Wrapper provides the AMBA AXI bus interface, which cannot be directly connected together. An axi2apb Bridge is required for connection as follows
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We choose apb_ bus_ m32_bridge module from Bus Bridge series ,so the APB master bus interface provided by the bus bride module is used to connect our IP as follows
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This experiment provides the corresponding AXI2ABP Bus Bridge basic file axi2apb.v module file: apb_bus_m32_bridge.v and apb_bus_m32_bridge.edf
The corresponding connection between the design case and the hardware platform (SP7021 motherboard and FPGA daughter board) pin is shown in the following table: 1: U20B on the motherboard is connected to J2 of the FPGA daughter board (Pin pin corresponding, such as 1-51 ...), providing the data transmission channel between the Plus1 main chip on the motherboard and the FPGA
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