Versions Compared

Old Version 17

changes.mady.by.user Wells Lu

Saved on

compared with

New Version Current

changes.mady.by.user Wells Lu

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Following this initialization phase, i-boot loads x-boot from external storage devices into SRAM and performs a checksum verification. If the verification passes, i-boot proceeds to execute x-boot.

Table of Contents

Table of Contents

Key

...

Features

  1. Output log at UART0 with a baud rate of 115,200 bps.

  2. UART0 pins can be turned off through an OTP bit.

  3. Read bootstrap pins IV_MX[6..3] to decide boot-device.

  4. Support for five boot devices: SPI-NOR flash, SPI-NAND flash, 8-bit NAND flash, eMMC, SD card, and USB flash drive (on either USB2.0 or USB3.0 port).

  5. Implementation of secure-boot with the ability to verify the digital signature of the x-boot image and decrypt it.

  6. Secure-boot activation controlled by an OTP bit.

  7. Support for warm-boot, enabling wake-up from deep-sleep mode.

  8. Support for the peripheral-reset signal (output from G_MX2).

Main

...

Flow

The i-boot flow initiates with the reset vector, followed by the execution of the "cpu_init" subroutine responsible for initializing the CPU. Next in the sequence is the "start_boot" subroutine, which sets up the C execution environment. The flow then advances to execute the "iboot_main" subroutine, serving as the C main function within i-boot.

...

It's essential to note that i-boot does not initialize DDR DRAM, rendering it temporarily unavailable. Hence, x-boot must be loaded into SRAM for execution.

...

Boot

...

Devices

i-boot Boot supports for 5 five boot devices. The following table lists the specifications or requirements of , each with specific specifications and requirements. Below is a detailed table outlining the specifications for each boot device:

Boot devices

Specifications

8-bit NAND

flash

  1. First block of 8-bit NAND flash The first block should contain Sunplus Boot Profile Header.

  2. x-boot image should be stored in 1K60 ECC sectors.

  3. x-boot image should be stored in 1K60 ECC sectors.

  4. Read Set read cycle-time is set to 240 nS.

  5. GPIO82 should be set to HIGH if for 3.0V NAND flash is used or , LOW if for 1.8V NAND flash is used.

eMMC device

  1. x-boot image should be stored at Boot Area Partition 1.

  2. Bus Set bus clock is set to 25 MHz.

  3. GPIO82 should be set to HIGH if for 3.0V IO power is used or , LOW if for 1.8V IO power is used.

SPI-NAND flash

  1. First block of SPI-NAND flash should contain Sunplus Boot Profile Header.

  2. x-boot image should be stored in 1K60 ECC sectors.

  3. Support for X1 and X2 position of SPI-NAND. First try positions. Attempt X1 position first and then proceed to X2 position.

  4. Bus Set bus clock is set to 11.2 MHz.

  5. GPIO82 should be set to HIGH if for 3.0V SPI-NAND flash is used or , LOW if for 1.8V SPI-NAND flash is used.

SPI-NOR flash

  1. x-boot image should be stored at offset 0x18000 (96Ki96KiB).

  2. Bus Set bus clock is set to 11.2 MHz.

  3. GPIO82 should be set to HIGH if for 3.0V SPI-NOR flash is used or , LOW if for 1.8V SPI-NOR flash is used.

SD card

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. The file ISPBOOOT.BIN should be stored in the root directory of the first or sole partition of the SD card.

  3. First or sole partition of the SD card The partition should be formatted to FAT32 or FAT16 formatfile-system.

  4. Bus Set bus clock is set to 5 MHz.

USB flash drive

  1. x-boot image should be stored at offset 0 of the file ISPBOOOT.BIN.

  2. The file ISPBOOOT.BIN should be stored in the root directory of first or sole partition of the USB flash drive.First

  3. or sole partition of the USB flash drive The partition should be formatted to FAT32 or FAT16 formatfile-system.

  4. Support high-speed read operation only

  5. Support USB flash drive on both USB2.0 or USB3.0 ports. Try Attempt USB3.0 port first and then proceed to USB2.0 port.

CPU Boot

...

Core and

...

Other Cores

CPU core 0 is serves as the boot core and is responsible for booting. It is , responsible for all boot processes from i-boot to Linux. Meanwhile, CPU core 1, 2, and 3 enter a spin state (enter wfe mode) after initializing itself until core 0 wake up them.

...

image-20240122-034050.pngImage Removed

Run Control of CPU (at bootcompat session) :

image-20240122-034202.pngImage Removedwithin i-boot after self-initialization, awaiting activation by core 0. The subsequent assembly code illustrates these processes.

Line 75~78: Read MPIDR to retrieve the CPU core id.

Line 79 ~ 80: Verify whether the core id is equal to 0 (indicating core 0). If ture, execute the jump to start_boot; otherwise (for core 1, 2, 3), proceed to A_cpu_wait.

Line 84 ~ 99: Retrieve the CPU Run Control field. If the field is equivalent to CPU_WAIT_INIT_VAL, continue a loop (spin) between line 91 ~ 96 (depicted by the red rectangle). If the field is equal to CPU_WAIT_A64_VAL, initiate a jump to A_go_AA_64 (line105). For any other field values, perform a jump to the specified address.

...

Each CPU core possesses its own CPU Run Control field, with each field being 32 bits wide and situated in SRAM.

...

The values of the CPU Run Control field are defined in the table below:

Values

Define

Descriptions

0xFFFFFFFF

CPU_WAIT_INIT_VAL

...

CPU continues spining (waiting)

0xFFFFFFFE

CPU_WAIT_A64_VAL

...

CPU goes to

...

x (address other than above)    // CPU goes to x

Bootstrap pins of SP7350

...

switch to 64-bit mode.

X

CPU jumps to address X directly.

CPU core 0 fills the specified value into the CPU Run Control field of the target core to wake it up.

Bootstrap Pins of SP7350

The state of bootstrap pins of SP7350 will be is read into bootstrap register (G0.31) at the moment that upon releasing power-on reset is released. Refer to definition of boot-strap pins of SP7350 in i-boot below:

Boot-strap pins of SP7350

Boot devices

MX6

MX5

MX4

MX3

MX2

MX1

MX0

1

1

1

1

1

x

x

eMMC boot

1

1

1

0

1

x

x

SPI-NAND boot

1

1

0

1

1

x

x

USB boot

1

1

0

0

1

x

x

SDC boot

1

0

1

1

1

x

x

SPI-NOR boot

1

0

0

0

1

x

x

8-bit NAND boot

Note:

  1. If MX1 = 0, the JTAG interface of CA55 of SP7350 will be enabled.

  2. If MX2 = 0, SP7350 will enter test mode. Always set to 1 for normal operation.

...

  1. .

i-boot Log and Explanation

Line 1: The banner (version) of i-boot

Line 4: Boot-mode is 0x1F (MX[6..2]), indicating eMMC boot.

Line 6: “[emmc_boot]” signifies that i-boot is executing the 'emmc boot' flow.

Line 11: The bus clock of eMMC is configured to 200kHz (divisor = 1789) for the IdentifyStorage command.

Line 15: The bus clock of eMMC is adjusted to 25MHz (divisor = 14) for subsequent Read and other commands.

Line 24: The magic number (signature of the x-boot image) is 0x54554258 ('XBUT').

Line 25: The length of the x-boot image is 0xAEA0 (44,704 bytes), excluding DDR training firmware.

Line 26: The checksum of the x-boot image is 0x2866.

Line 27: The secure flag is 0, indicating non-secure boot.

Line 29: The image checksum is successfully verified.

Line 31: Proceeding to execute x-boot.

Code Block
+++iBoot v1.0 Oct 18 2022 13:51:18
[d] iboot.c:134
[d] iboot.c:157
mode=0x0000001F

[emmc_boot]
dev=2 pin=1
.[d] bootmain.c:136
...[d] drv_sd_mmc.c:21
InitChipCtrl
busclk=200000 div=1789
[d] drv_sd_mmc.c:23
IdentifyStorage
[d] hal_sd_mmc.c:478
busclk=25000000 div=14
[d] hal_sd_mmc.c:1709
[d] drv_sd_mmc.c:33
[d] iboot.c:526
mg=0x54554258
len=0x0000AEA0
chk=0x0000F3D7
[d] iboot.c:557
[d] iboot.c:567
mg=0x54554258
len=0x0000AEA0
chk=0x0000F3D7
flg=0x00000000
[d] bootmain.c:559
img chksum correct

boot!
.15522