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1.2.2 Minimizing the area of a current loop
Minimizing Keeping the area of a current loop holds significant importance in electronic circuit board design due to the following reasons:
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Improving Signal Integrity: In high-speed digital circuits, minimizing the area of current loops is crucial to mitigate inductive effects. These effects can lead to signal integrity issues such as distortion, crosstalk, and jitter. By reducing the loop area, the associated inductance is decreased, resulting in enhanced signal quality and more reliable data transmission.
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as small as possible is a fundamental principle in PCB design for several reasons:
Minimize Electromagnetic Interference (EMI): A smaller current loop functions akin to an antenna, emitting electromagnetic radiation. According to Maxwell's equations, the strength of the magnetic field generated by a current is directly proportional to the area enclosed by the current loop. Therefore, minimizing the loop area also reduces the emitted electromagnetic interference (EMI).
Various techniques are employed to minimize the area of current loops.
1.2.2.1 Provide Signal Return Path
At higher frequencies, the return current naturally seeks the path of least impedance, typically flowing beneath the ground plane. In the illustration below, the forward current (indicated by the blue arrow) travels along a trace from the signal source to its destination, while the return current (highlighted by the red arrow) follows beneath the ground plane, flowing from the sink back to the source.
reduces the area enclosed by the loop, which in turn decreases the loop's magnetic field. This helps to minimize electromagnetic interference both within the circuit and with neighboring circuits, leading to better signal integrity and reduced susceptibility to noise.
Reduced Inductance: A smaller loop area corresponds to lower loop inductance. Inductance opposes changes in current flow, so minimizing it helps improve the circuit's response time and stability. This is particularly important in high-frequency circuits where even small inductances can have significant effects.
Decreased Radiated Emissions: By minimizing the size of the current loop, you also reduce the extent to which the circuit radiates electromagnetic energy. This is especially important for compliance with electromagnetic compatibility (EMC) regulations, which limit the amount of electromagnetic radiation devices can emit.
Less Crosstalk: Smaller current loops reduce the likelihood of crosstalk between adjacent signal traces. Crosstalk occurs when the magnetic field generated by one trace induces a voltage in an adjacent trace, leading to signal degradation or interference.
Overall, keeping the current loop as small as possible helps to maintain signal integrity, minimize interference, and improve the performance and reliability of the PCB design. Various techniques are employed to minimize the area of current loops.
1.2.2.1 Provide Signal Return Path
At higher frequencies, the return current naturally seeks the path of least impedance, typically flowing beneath the ground plane. In the illustration below, the forward current (indicated by the blue arrow) travels along a trace from the signal source to its destination, while the return current (highlighted by the red arrow) follows beneath the ground plane, flowing from the sink back to the source.
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However, the presence of slots or gaps in the ground plane can disrupt these currents, causing them to circumvent the slot area, as shown in the figure below.
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Changing layers is typically unavoidable when routing on a 4-layer PCB. As depicted below, transitioning from Layer 1 to Layer 4 (or vice versa) occurs in the midst of source and sink devices. In such cases, without a bypass capacitor to facilitate high-frequency signal flows, the return current continues to flow through the ground plane. Consequently, the combined current loop area (A2 + A3) significantly increases compared to the area A shown in the preceding figure. This expansion results in heightened electromagnetic field strength and an increased potential for electromagnetic interference.
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One solution is to incorporate The simplest way to mitigate this issue is to relocate the via closer to either the source or the sink. As depicted in the figure below, the via is repositioned near the sink. This adjustment significantly reduces the combined current loop area (A4 + A5), thereby ensuring that the electromagnetic field remains at a lower level.
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If relocating the via is not feasible, mitigating this issue can be achieved by incorporating a bypass capacitor near the transition point, where one end connects to the ground plane and the other end connects to the power plane. As depicted below, the return current flows through the bypass capacitor back to the ground plane. This arrangement ensures that the current loop area (A4 A6 + A5A7) remains nearly identical to area A in the preceding figure, thereby maintaining a consistent electromagnetic field level.
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Another solution involves adding a ground trace adjacent to the original net on Layer 4, providing a path for the return current. It's essential to terminate the ground trace with ground vias at both ends to ensure proper grounding and minimize impedance.
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For a single-end signal with 50Ω 50 Ω impedance on Layer 1, set the trace width to 5 mils and clearance to 10 mils.
For a differential-pair signal with 90Ω 90 Ω differential impedance on Layer 1, set the trace width to 4.5 mils and clearance to 6 mils.
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These target impedance values are crucial for maintaining stable and reliable power delivery across different power domains, ensuring the system operates optimally.
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Refer to the Power Distribution Network (PDN) simulation of the VDD_CA55 on the SP7350 Evaluation Board conducted using Ansys software.
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The simulation results confirm that the impedance meets the criteria of being less than 40.0 mΩ, ensuring compliance with the design specifications.
2.3 DDR SDRAM
Routing traces for DDR SDRAM requires careful planning and adherence to specific guidelines to maintain signal integrity and performance. Here are the general guidelines for routing traces for DDR SDRAM:
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Adhering to these target impedance values ensures optimal performance and reliability of the DDR PHY within the PCB design.
2.3.1.2 DQ to DQ Mismatch Within a Byte
Skew limit: < 200ps
Recommended skew: < 20psRefer to the Power Distribution Network (PDN) simulation of the DRAM_VDD on the SP7350 Evaluation Board conducted using Ansys software.
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The simulation results confirm that the impedance meets the criteria of being less than 38.6 mΩ, ensuring compliance with the design specifications.
Refer to the Power Distribution Network (PDN) simulation of the DRAM_VDDQ on the SP7350 Evaluation Board conducted using Ansys software.
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The simulation results confirm that the impedance meets the criteria of being less than 39.0 mΩ, ensuring compliance with the design specifications.
2.3.1.
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2 DQ to
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DQ Mismatch Within a Byte
Skew limit: DQS ±100ps< 200 pS
Recommended skew: DQS ±10ps< 20 pS
2.3.1.3 DQ to DQS Skew
Skew limit: DQS ±100 pS
Recommended skew: DQS ±10 pS
2.3.1.4 CS, CKE, ODT, CA to CK Skew
Recommended skew: CK ±10ps±10 pS
Skew limit can be relaxed if the timing budget and simulation results indicate that there is adequate margin.
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Skew limit: -0.5 to +5.47 clock cycles
Recommended skew: CK ±60ps±60 pS
2.3.1.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.1.7 Trace Impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT and CA: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.1.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Eye height: 140mV140 mV
Setup time: 67.1ps 1 pS (SDRAM contributions* and PHY contributions**)
Hold time: 69.8ps 8 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 73.8ps 8 pS (SDRAM contributions* and PHY contributions**)
Hold time: 76.2ps 2 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 61.2ps 2 pS (SDRAM contributions* and PHY contributions**)
CS, ODT and CA (rectangular mask):
Eye height: 155mV155 mV
Setup time: 159.7ps 7 pS (SDRAM contributions* and PHY contributions**)
Hold time: 159.7ps 7 pS (SDRAM contributions* and PHY contributions**)
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Referring to reference layout of Layer 1 (Top) below, it is imperative to maintain a controlled impedance of 100Ω 100 Ω for the four specified differential pairs, while single-end signals should adhere to a 50Ω 50 Ω impedance standard. The sequence of the four differential pairs, from left to right, is as follows: (DRAM_SDQS1_T_A, DRAM_SDQS1_C_A), (DRAM_CK_C_A, DRAM_CK_T_A), (DRAM_CK_T_B, DRAM_CK_C_B), and (DRAM_SDQS1_T_B, DRAM_SDQS1_C_B).
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Refer to reference layout of Layer 3 (L3_S) below, similarly, the impedance of the two specified differential pairs should be maintained at 100Ω100 Ω, while other single-end signals should adhere to a 50Ω 50 Ω impedance standard. These two differential pairs, arranged from left to right, are: (DRAM_SDQS0_T_A, DRAM_SDQS0_C_A), and (DRAM_SDQS0_C_B, DRAM_SDQS0_T_B).
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Referring to reference layout of Layer 6 (Bottom) below, the prescribed impedance for all single-end signals is 50Ω50 Ω, ensuring consistency and optimal signal integrity throughout the design. Note that bypass capacitors for PHY and SDRAM are all placed at this layer.
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2.3.2.2 DQ to DQ Mismatch
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.2.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.2.4 CS, CKE, ODT, Command and Address to CK Skew
Skew limit: 0 to 1UI*
Recommended skew: CK ±25ps±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
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Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85ps±85 pS
2.3.2.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.2.7 Trace Impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT, command and address: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.2.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Eye height: 120mV120 mV
Setup time: 62.7ps 7 pS (SDRAM contributions* and PHY contributions**)
Hold time: 66ps 66 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 77.6ps 6 pS (SDRAM contributions* and PHY contributions**)
Hold time: 81ps 81 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 39.8ps 8 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels:
510mV 510 mV (AC input logic low)
690mV 690 mV (AC input logic high)
Setup time: 176.8ps 8 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
535mV 535 mV (DC input logic low)
665mV 665 mV (DC input logic high)
Hold time: 180.8ps 8 pS (SDRAM contributions* and PHY contributions**)
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2.3.3.2 DQ to DQ Mismatch
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.3.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.3.4 CS, CKE, ODT, Command and Address to CK Skew
Skew limit: 0 to 1UI*
Recommended skew: CK ±25ps±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
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Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85ps±85 pS
2.3.3.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.3.7 Trace impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT, command and address: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.3.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Setup levels:
615mV 615 mV (AC input logic low)
885mV 885 mV (AC input logic high)
Setup time: 136.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
650mV 650 mV (DC input logic low)
850mV 850 mV (DC input logic high)
Hold time: 124.3ps 3 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 123.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold time: 166.5ps 5 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 43ps 43 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels: 625mV 625 mV (AC input logic low)
875mV 875 mV (AC input logic high)
Setup time: 270.1ps 1 pS (SDRAM contributions* and PHY contributions**)
Hold levels: 650mV 650 mV (DC input logic low)
850mV 850 mV (DC input logic high)
Hold time: 217.2ps 2 pS (SDRAM contributions* and PHY contributions**)
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2.3.4.2 DQ to DQ Mismatch
Skew limit: < 200ps200 pS
Recommended skew: < 20ps20 pS
2.3.4.3 DQ to DQS Skew
Skew limit: DQS ±100ps±100 pS
Recommended skew: DQS ±10ps±10 pS
2.3.4.4 CS, CKE, ODT, Command and Address to CK Skew
Skew limit: 0 to 1UI*
Recommended skew: CK ±25ps±25 pS
*Programmable delay can be added to 4-bit groups of AC signals (ACX4-0 ~ ACX4-9).
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Skew limit: -1.0 to +5.97 clock cycles
Recommended skew: CK ±85ps±85 pS
2.3.4.6 DQS/DQS# and CK/CK# Intra-pair Skew
Maximum intra-pair skew: 3ps3 pS
2.3.4.7 Trace Impedance
DQ: 50Ω 50 Ω ±10%
DQS (diff.): 100Ω 100 Ω ±10%
DM: 50Ω 50 Ω ±10%
CS, CKE, ODT, command and address: 50Ω 50 Ω ±10%
CK (diff.): 100Ω 100 Ω ±10%
2.3.4.8 SI Criteria
The corresponding threshold levels are defined in JEDEC standard. Timing budgets should include both SDRAM contributions and PHY contributions, which are listed below.
Data write (rectangular mask):
Setup levels:
540mV 540 mV (AC input logic low)
810mV 810 mV (AC input logic high)
Setup time: 136.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
575mV 575 mV (DC input logic low)
775mV 775 mV (DC input logic high)
Hold time: 124.3ps 3 pS (SDRAM contributions* and PHY contributions**)
Data read (diamond mask):
Eye height: 140mV140 mV
Setup time: 123.5ps 5 pS (SDRAM contributions* and PHY contributions**)
Hold time: 166.5ps 5 pS (SDRAM contributions* and PHY contributions**)
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Clock jitter: < 43ps 43 pS (SDRAM contributions* and PHY contributions**)
CS, CKE, ODT, command and address (rectangular mask):
Setup levels:
550mV 550 mV (AC input logic low)
800mV 800 mV (AC input logic high)
Setup time: 270.1ps 1 pS (SDRAM contributions* and PHY contributions**)
Hold levels:
575mV 575 mV (DC input logic low)
775mV 775 mV (DC input logic high)
Hold time: 217.2ps 2 pS (SDRAM contributions* and PHY contributions**)
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2.4.1.3 Trace Impedance
D[3:0], CSN, CLK: 50Ω 50 Ω ±10%
2.4.2 SPI-NAND Flash
2.4.2.1 General Rules
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2.4.2.3 Trace Impedance
D[3:0], CSN, CLK: 50Ω 50 Ω ±10%
2.4.3 8-bit NAND Flash
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2.4.3.3 Trace Impedance
Trace Impedance: 50Ω 50 Ω ±10%
2.4.4 eMMC Device
2.4.4.1 General Rules
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CLK, CMD, DQ and DS signals : 50Ω 50 Ω ±10%
2.4.4.4 Reference Layout
Referring to reference layout of Layer 1 (Top) below, all eMMC nets initially originate from SP7350 and traverse Layer 1. It is important to maintain a controlled impedance of 50Ω 50 Ω for all eMMC nets whenever possible.
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2.4.5.2 DP/DM Differential-pair Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.5.3 Trace Impedance
DP/DM differential-pair: 90Ω 90 Ω ±10%
2.4.5.4 Reference Layout
In the reference layout below, the data differential pair of USB 2.0 is initially routed at Layer 3, and subsequently transition to Layer 6 towards a connector. It is crucial to maintain a controlled differential impedance of 90Ω 90 Ω for this pair.
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2.4.6 USB3.0
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2.4.6.2 TX or RX Differential-pairs Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.6.3 DP/DM Differential-pair Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.6.4 Trace Impedance
TX or RX differential-pairs: 90Ω 90 Ω ±10%
DP/DM differential-pair: 90Ω 90 Ω ±10%
2.4.6.5 Power loop inductance
USB3_AVDD08: < 2.4nH4 nH
USB3_DVDD08: < 2.4nH4 nH
USB3_VDD33: < 2.8nH8 nH
2.4.6.6 Reference Layout
In the reference layout below, the six differential pairs of USB 3.0 are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. It is crucial to maintain a controlled differential impedance of 90Ω 90 Ω for all pairs. From top to bottom, the differential pairs are: (USB30_TX1_DP_0, USB30_TX1_DM_0), (USB30_RX1_DP_0, USB30_RX1_DM_0), (USB30_TX0_DM_0, USB30_TX0_DP_0), (USB30_RX0_DM_0, USB30_RX0_DP_0), and (USB30_DM, USB30_DP).
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CLK, CMD, D[3:0] signals : 50Ω 50 Ω ±10%
2.4.7.4 Reference Layout of SD Card
In the reference layout below, the six nets of the SD card are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50Ω 50 Ω for all SD card signals throughout.
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In the reference layout below, the six nets of the SDIO are initially routed at Layer 1, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50Ω 50 Ω for all SDIO signals throughout.
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2.4.8.2 Data Differential-pairs Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.8.3 Clock Differential-pair Mismatch
Maximum intra-pair skew: 1ps1 pS (~6mil)
2.4.8.4 Data to Clock Skew
Channel skew limit: clock ±66ps±66 pS
2.4.8.5 Trace Impedance
Data and clock differential-pairs: 100Ω 100 Ω ±10%
2.4.8.6 Reference Layout of MIPI-
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RX2
In the reference layout below, the three differential pairs nets of the MIPI-RX4 RX2 are initially routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 towards a near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI4MIPIRX2_DP2, MIPIRX2_DN2), (MIPIRX2_DN0, MIPIRX2_DP0, MIPI4_DN0), (MIPI4_SP, MIPI4_SN), and (MIPIRX2_DP3, MIPIRX2_DN3).
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From top to bottom, the differential pairs are: (MIPIRX2_CN, MIPIRX2_CP), and (MIPI4MIPIRX2_DP1, MIPI4MIPIRX2_DN1).
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2.4.8.7 Reference Layout of MIPI-
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RX3
In the reference layout below, the five differential pairs nets of the MIPI-RX5 RX3 are initially routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 towards a near the connector. It is crucial to maintain a controlled differential impedance of 100Ω 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI5MIPIRX3_DN2DP0, MIPI5_DP2), (MIPI5_DN0, MIPI5_DP0MIPIRX3_DN0), and (MIPI5MIPIRX3_SPCN, MIPI5MIPIRX3_SN), (MIPI5CP).
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The differential pair is: (MIPIRX3_DN1, MIPI5MIPIRX3_DP1).
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2.4.8.8 Reference Layout of MIPI-RX4
In the reference layout below, and (MIPI5_DP3, MIPI5_DN3).
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the three differential pairs of MIPI-RX4 are initially routed at Layer 1, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI4_DP0, MIPI4_DN0), (MIPI4_SP, MIPI4_SN), and (MIPI4_DP1, MIPI4_DN1).
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2.4.8.9 Reference Layout of MIPI-RX5
In the reference layout below, the five differential pairs of MIPI-RX5 are initially routed at Layer 3, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPI5_DN2, MIPI5_DP2), (MIPI5_DN0, MIPI5_DP0), (MIPI5_SP, MIPI5_SN), (MIPI5_DN1, MIPI5_DP1), and (MIPI5_DP3, MIPI5_DN3).
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2.4.8.8 Reference Layout of MIPI-TX
In the reference layout below, the five differential pairs of MIPI-TX are initially routed at Layer 1, and subsequently transition to Layer 6 near the connector. It is crucial to maintain a controlled differential impedance of 100 Ω for all pairs. From top to bottom, the differential pairs are: (MIPITX_DP3, MIPITX_DN3), (MIPITX_DP2, MIPITX_DN2), (MIPITX_SP, MIPITX_SN), (MIPITX_DP1, MIPITX_DN1), and (MIPITX_DP0, MIPITX_DN0).
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2.4.9 Ethernet Interface (RGMII)
2.4.9.1 General Rules
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs, and crossovers in routing, as these can introduce impedance mismatches and signal reflections.
2.4.9.2 TXD[3:0] and TXEN to TXC Skew
Skew of TXD[3:0] and TXEN to TXC signals: ±100 mil
2.4.9.3 RXD[3:0] and RXDV to RXC Skew
Skew of RXD[3:0] and RXDV to RXC signals: ±100 mil
2.4.9.4 Trace Impedance
TXD[3:0], TXEN, TXC, RXD[3:0], RXDV and RXC signals: 50 Ω ±10%
2.4.9.5 Reference Layout
In the reference layout below, the five differential pairs of MIPI-TX are initially nets of the RGMII are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 towards a near the connector. It is crucial to maintain a controlled differential impedance of 100Ω for all pairs. From top to bottom, the differential pairs are: (MIPITX_DP3, MIPITX_DN3), (MIPITX_DP2, MIPITX_DN2), (MIPITX_SP, MIPITX_SN), (MIPITX_DP1, MIPITX_DN1), and (MIPITX_DP0, MIPITX_DN0).
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Please maintain a controlled impedance of 50 Ω for all RGMII signals throughout.
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2.4.
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10 Ethernet Interface (
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RMII)
2.4.
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10.1 General Rules
For single-ended signals, ensure that trace lengths run parallel to each other smoothly to maintain signal integrity. Avoid sharp corners, stubs , and crossovers in routing, as these can introduce impedance mismatches and signal reflections.
2.4.9.2 TXD[3:0] and TXEN to TXC Skew
Skew of TXD[3:0] and TXEN to TXC signals: ±100 mil
2.4.9.3 RXD[3:0] and RXDV to RXC Skew
Skew of RXD[3:0] and RXDV to RXC signals: ±100 milin routing, as these can introduce impedance mismatches and signal reflections.
2.4.
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10.
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2 Trace Impedance
TXD[31:0], TXEN, TXCREF_CLK, RXD[31:0] , RXDV and RXC CRS_DV signals : 50Ω ±10%
2.4.9.5 Reference Layout
In the reference layout below, the nets of the RGMII are routed at Layer 1 and Layer 3, and subsequently transition to Layer 6 towards a connector. Please maintain a controlled impedance of 50Ω for all RGMII signals throughout.
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50 Ω ±10%