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The aim of this document is to explain how to setup pins of SP7350 in device-tree source. SP7350 has 106 general purpose IO (GPIO) pins which are multiplexed with other special functions, like eMMC device, SPI-NOR flash, SPI-NAND flash, Ethernet PHY (RGMII or RMII interface), UART, I2C pins, and etc.
The following sections will explain how to setup GPIOs and special function pins in device-tree source file. Note that the same device-tree source file is used by U-Boot and Linux in SP7350. Both Pinctrl drivers support generic helper bindings.
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Table of Contents
function
The function to be applied on particular pins or groups. See section "Functions" below.
pins
The pins to apply the properties to. See section "Pins" below.
groups
The groups to apply the properties to. See section "Groups" below.
Functions
We define a bunch of functions as listed in appendix Function-group Table below.
Pins
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Table of Contents |
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IO Pins
In the Linux, name of IO pin is in form of GPIO(id), like GPIO0, GPIO1, GPIO2, GPIO99…, GPIO105, and etc. There are two kinds of GPIO pins. One is 1.8V GPIO pins, and the other is 1.8V/3.0V Dual Voltage IO (DVIO) pins. Beside configure 1.8V or 3.0V power to power supply of a DVIO group in your circuit boards (hardware), you need to setup Voltage Mode Select (MS control) in device-tree source. Refer to groups of GPIO and DVIO in appendix GPIO Table below in details.
Groups
We define a bunch of groups as listed in appendix Function-group Table below.
Voltage Mode Select
For These IO pins of SP7350 are categorized, based on their operating voltage, into two groups:
Single-supply IO pins: The IO pins operate on a single power supply, specifically at 1.8V.
Dual-supply IO pins: The IO pins offer a dual power supply option, supporting both 1.8V and 3.0V. These pins are referred to as DVIO pins in the subsequent sections.
Refer to table below for a breakdown of power domain, supplying voltage, pin name (hardware pin name), supplying power pins of all IO pins of SP7350:
GPIO # | Power domain | Type | Pin name | Power-supply |
0 - 19 | Main | 1.8V GPIO | G_MX0 - G_MX19 | VDDPST18_GPIO |
20 | 1.8V/3.0V |
...
DVIO |
...
Properties | Pins | Value |
---|---|---|
sunplus,ms-dvio-group-0 | G_MX21~G_MX27 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-group-1 | G_MX20, G_MX28~G_MX37 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-ao-group-0 | AO_MX0~AO_MX9 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-ao-group-1 | AO_MX10~AO_MX19 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-ao-group-2 | AO_MX20~AO_MX29 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
pinmux
Panel | ||||||
---|---|---|---|---|---|---|
| ||||||
Here we only list the generic pinmux methods supported by SP7350. |
Set a single pin to function "GPIO"
set "GPIO0" to function"GPIO"
Code Block | ||
---|---|---|
| ||
pinmux_example {
function = "GPIO";
pins = "GPIO0";
}; |
Set several pins to function "GPIO"
set "GPIO0" and "GPIO1" to function"GPIO"
Code Block | ||
---|---|---|
| ||
pinmux_example {
function = "GPIO";
pins = "GPIO0", "GPIO1";
}; |
Set a group of pins to a particular function
set group "UART0_X1" to function "UART0"
Code Block | ||
---|---|---|
| ||
pinmux_example {
function = "UART0";
groups = "UART0_X1";
}; |
pinconf
Info |
---|
Here we only list the generic pin configuration parameters supported by SP7350. |
bias-disable
description
Disable any pin bias on the pin.
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example {
:
:
bias-disable;
:
:
}; |
bias-high-impedance
description
The pin will be set to a high impedance mode, also know as "third-state" (tri-state) or "high-Z" or "floating".
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example {
:
:
bias-high-impedance;
:
:
}; |
bias-pull-up
description
The pin will be pulled up.
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example {
:
:
bias-pull-up;
:
:
}; |
bias-pull-down
description
...
G_MX20 | VDDPST3018_DVIO_2 | ||
21 - 27 | G_MX21 - G_MX27 | VDDPST3018_DVIO_1 | |
28 - 37 | G_MX28 - G_MX37 | VDDPST3018_DVIO_2 | |
38 - 43 | G_MX38 - G_MX43 | AVDDIO_3018_SD | |
44 - 49 | G_MX44 - G_MX49 | AVDDIO_3018_SDIO | |
50 - 59 | CM4 (AO) | AO_MX0 - AO_MX9 | VDDPST3018_DVIO_AO_1 |
60 - 69 | AO_MX10 - AO_MX19 | VDDPST3018_DVIO_AO_2 | |
70 - 79 | AO_MX20 - AO_MX29 | VDDPST3018_DVIO_AO_3 | |
80 - 98 | 1.8V GPIO | AO_MX30 - AO_MX48 | VDDPST18_GPIO_AO |
99 - 105 | IV_MX0 - IV_MX6 |
Voltage Mode Select
Beyond configuring the 1.8V or 3.0V power to supply pins of a DVIO group in circuit boards (hardware), setting up the voltage mode select (ms control) control-bits is crucial for the normal operation of IO pins. The following properties configure voltage mode select control-bits in the Device Tree Source (DTS) file:
Properties | Pins | Value |
---|---|---|
sunplus,ms-dvio-group-0 | G_MX21~G_MX27 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-group-1 | G_MX20, G_MX28~G_MX37 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-ao-group-0 | AO_MX0~AO_MX9 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-ao-group-1 | AO_MX10~AO_MX19 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
sunplus,ms-dvio-ao-group-2 | AO_MX20~AO_MX29 | “3V0“ for 3.0V; “1V8“ for 1.8V. |
These properties should be set in the pinctrl node in the DTS file. For example:
Code Block | ||
---|---|---|
| ||
pctl: pinctrl@f8800080 {
:
:
sunplus,ms-dvio-group-0 = “1V8“;
sunplus,ms-dvio-group-1 = “3V0“;
sunplus,ms-dvio-ao-group-2 = “1V8“;
:
}; |
Default voltage is “3V0”.
Pin Multiplexing Nodes
function - the multiplex function to select.
groups - the list of groups to select with this function. Either this or "pins" must be specified.
pins - the list of pins to select with this function. Either this or "groups" must be specified.
Refer to examples below:
Set a Single Pin to GPIO function
Code Block | ||
---|---|---|
| ||
pinmux_example {
function = "GPIO";
pins = "GPIO0";
}; |
Set pin GPIO0 to GPIO function.
Set Several Pins to GPIO function
Code Block | ||
---|---|---|
| ||
pinmux_example {
function = "GPIO";
pins = "GPIO0", "GPIO1", "GPIO10";
}; |
Set pins GPIO0, GPIO1, GPIO10 to GPIO function.
Set a Group of Pins to a Specified Function
Code Block | ||
---|---|---|
| ||
pinmux_example {
function = "UART0";
groups = "UART0_X1";
}; |
Set a group of pins, whose group-name is UART0_X1, to UART0 function. Actually, the group includes pins GPIO50 and GPIO51.
Refer to Function-group Table in appendix.
Pin Configuration Nodes
Info |
---|
Here we only list the generic pin configuration parameters supported by SP7350. |
bias-disable
description
Disable any pin bias on the pin.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : bias-pull-downdisable; : : }; |
...
bias-
...
high-
...
impedance
description
The pin will be driven with open drain (open collector) which means it is usually wired with other output ports which are then pulled up with an external resistor. Setting this config will enable open drain mode.set to a high impedance mode, also know as "third-state" (tri-state) or "high-Z" or "floating".
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : drivebias-openhigh-drainimpedance; : : }; |
...
bias-
...
pull-
...
up
description
The pin will sink or source at most the current passed as argumentbe pulled up.
argument
The argument is in uAignored.
See linux/kernel/include/dt-bindings/pinctrl/sppctl-config-sp7350.h for selectable argument.
usage
...
language | c |
---|
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usage
Code Block | ||
---|---|---|
| ||
pinconf_example { : : /* source current 1100uA for GPIO*/ drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_1100_IOL_1100UA>bias-pull-up; : : }; |
bias-pull-down
description
The pin will be pulled down.
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example { : : /* source current 5100uA for DVIO*/bias-pull-down; : : }; |
drive-
...
open-drain
description
Enable the pin's inputThe pin will be driven with open drain (open collector) which means it is usually wired with other output ports which are then pulled up with an external resistor. Setting this config will enable open drain mode.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : inputdrive-open-enabledrain; : : }; |
...
drive-strength-
...
microamp
description
Disable the pin's inputThe pin will sink or source at most the current passed as argument.
argument
The argument is ignored.
usage
...
in uA.
See linux/kernel/include/dt-bindings/pinctrl/sppctl-config-sp7350.h for selectable argument.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example { : : input-disable/* source current 1100uA for GPIO*/ drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_1100_IOL_1100UA>; : : }; |
input-schmitt-enable
...
This will configure an input pin to run in Schmitt-trigger mode.
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example { : : input-schmitt-enable; :/* source current 5100uA for DVIO*/ : drive-strength-microamp = <SPPCTRL_DVIO_DRV_IOH_5100_IOL_6200UA>; : : }; |
input-
...
enable
description
This will disable Enable the pin's Schmitt-trigger modeinput.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : input-schmitt-disableenable; : : }; |
...
input-
...
disable
description
This will enable Disable the pin's output mode without driving a value thereinput.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : outputinput-enabledisable; : : }; |
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input-schmitt-
...
enable
description
This will disable the pin's output configure an input pin to run in Schmitt-trigger mode.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : outputinput-schmitt-disableenable; : : }; |
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input-schmitt-
...
disable
description
This will configure the pin as output and drive high level on the line.disable the pin's Schmitt-trigger mode.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : outputinput-schmitt-highdisable; : : }; |
output-
...
enable
description
This will configure enable the pin as output and drive low level on the line's output mode without driving a value there.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : output-lowenable; : : }; |
...
output-disable
description
This will invert disable the pin's input value. High level as 0, Low level as 1.output mode.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : sunplus,input-invert-enableoutput-disable; : : }; |
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output-
...
high
description
This will invert configure the pin 's output value. 1 as low level, 0 as high levelas output and drive high level on the line.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : sunplus,output-invert-enablehigh; : : }; |
...
output-low
description
This will normalize configure the pin 's input value. High level as 1, Low level as 0as output and drive low level on the line.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : sunplus,input-invert-disableoutput-low; : : }; |
sunplus,
...
input-invert-
...
enable
description
This will normalize invert the pin's output input value. 1 as high level, 0 as low levelHigh level as 0, Low level as 1.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : sunplus,outputinput-invert-disableenable; : : }; |
sunplus,
...
output-
...
invert-
...
enable
description
The pin will be pulled up strongly.
...
This will invert the pin's output value. 1 as low level, 0 as high level.
argument
The argument is ignored.
...
Code Block | ||
---|---|---|
| ||
pinconf_example { : : sunplus,biasoutput-stronginvert-pull-upenable; : : }; |
DTS
Device-tree source files of SP7350 are located in linux/kernel/arch/arm64/boot/dts/sunplus/.
Here lists all files for SP7350 boards:
Boards | Device-tree source files |
C3V-W EVB | sp7350-ev.dts |
Example
Voltage Mode Select
...
sunplus,input-invert-disable
description
This will normalize the pin's input value. High level as 1, Low level as 0.
argument
The argument is ignored.
usage
Code Block | ||||
---|---|---|---|---|
| pctl
| |||
pinconf_example { : pinctrl@f8800080 { : compatible = "sunplus,sp7350-pctl"input-invert-disable; : : }; |
sunplus,
...
output-
...
invert-disable
description
This will normalize the pin's output value. 1 as high level, 0 as low level.
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example { : sunplus,ms-dvio-group-1 = "1V8";: sunplus,msoutput-dvio-ao-group-0 = "1V8"invert-disable; sunplus,ms-dvio-ao-group-1 = "3V0";: : }; |
sunplus,
...
bias-
...
strong-
...
pull-up
description
The pin will be pulled up strongly.
Note |
---|
For GPIO only, excluding DVIO. |
argument
The argument is ignored.
usage
Code Block | ||
---|---|---|
| ||
pinconf_example {
:
:
sunplus,bias-strong-pull-up;
:
:
}; |
In this example, DVIO groups 0 and 1 are configured to operate at 1.8V, while DVIO AO group 0 is designated with a voltage setting of 1.8V. Conversely, DVIO AO groups 1 and 2 are specifically set to operate at 3.0V. It is crucial to note that in the absence of a specified selection, the default voltage for these groups is set to 3.0V.
GPIO
SP7350 has 106 general purpose IO (GPIO) pins. Most of them are multiplexed with other special function pins. This section explains how to modify device-tree source file to set up GPIO pins as digital input or output pins.
Define GPIO in device-tree source file
Every single device has a node in device-tree source (dts) file in Linux. Property pinctrl-0 (or pinctrl-1, pinctrl-2,… if a device has more states) is used to point at pin configuration node within pin controller (node pinctrl@f8800080 in SP7350). Pin configuration nodes (sub-nodes in node pinctrl@f8800080 ) define the actual pins assignment.
...
DTS Files
Device-tree source files of SP7350 are located in linux/kernel/arch/arm64/boot/dts/sunplus/.
Here lists all files for SP7350 boards:
Boards | Device-tree source files |
C3V-W Evaluation Board | sp7350-ev.dts |
C3V-W Demo Board | sp7350-dm.dts |
Example
Voltage Mode Select
For 1.8V/3.0V Dual Voltage IO (DVIO) pins, we need to select their voltage in pinctrl top node in DTS file. For example,
Code Block | ||
---|---|---|
| ||
pctl: pinctrl@f8800080 {
compatible = "sunplus,sp7350-pctl";
:
:
sunplus,ms-dvio-group-0 = "1V8";
sunplus,ms-dvio-group-1 = "1V8";
sunplus,ms-dvio-ao-group-0 = "1V8";
sunplus,ms-dvio-ao-group-1 = "3V0";
sunplus,ms-dvio-ao-group-2 = "3V0";
:
:
}; |
In this example, DVIO groups 0 and 1 are configured to operate at 1.8V, while DVIO AO group 0 is designated with a voltage setting of 1.8V. Conversely, DVIO AO groups 1 and 2 are specifically set to operate at 3.0V. It is crucial to note that in the absence of a specified selection, the default voltage for these groups is set to 3.0V.
GPIO
SP7350 has 106 general purpose IO (GPIO) pins. Most of them are multiplexed with other special function pins. This section explains how to modify device-tree source file to set up GPIO pins as digital input or output pins.
Define GPIO in device-tree source file
Every single device has a node in device-tree source (dts) file in Linux. Property pinctrl-0 (or pinctrl-1, pinctrl-2,… if a device has more states) is used to point at pin configuration node within pin controller (node pinctrl@f8800080 in SP7350). Pin configuration nodes (sub-nodes in node pinctrl@f8800080 ) define the actual pins assignment.
Users need to add properties pinctrl-names and pinctrl-0 to a node (device) in device-tree source file to set up GPIOs as digital input or output pins for a device . For example:
Code Block | ||
---|---|---|
| ||
u3phy0: uphy@f80bd000 {
:
:
pinctrl-names = "default";
pinctrl-0 = <&typec_pins>;
typec-gpios = <&pctl 98 GPIO_ACTIVE_HIGH>;
:
:
}; |
where property pinctrl-0 sets up pins of uphy@f80bd000 device for "default" state. It is a handle (an address) to sub-node of pin-controller node.
Property typec-gpios defines one GPIO pin to GPIO98 of pin controller. Linux driver can get GPIO descriptors using the property. pctl is a handle (an address) to pin controller.
The following device-tree source of SP7350 shows definitions of sub-node pinmux_typec-pins of node pinctrl@f8800080.
Code Block | ||
---|---|---|
| ||
typec_pins: pinmux_typec-pins {
function = "GPIO";
pins = "GPIO98";
}; |
Setting GPIO Characteristics
GPIO pins' characteristics, such as setting them to high, low, or configuring additional features, can also be directly specified within the pin node. For instance, we extend the previous example to add GPIO0 and GPIO1 and configure them as input and output, respectively. We introduce the extra_gpio_pins node label after typec_pins:
Code Block | ||
---|---|---|
| ||
u3phy0: uphy@f80bd000 {
:
:
pinctrl-names = "default";
pinctrl-0 = <&typec_pins &extra_gpio_pins>;
typec-gpios = <&pctl 98 GPIO_ACTIVE_HIGH>;
:
:
}; |
Add extra_gpio-pins node and label as shown below:
Code Block | ||
---|---|---|
| ||
u3phy0typec_pins: uphy@f80bd000pinmux_typec-pins { function = "GPIO"; pins = "GPIO98"; }; extra_gpio_pins: extra_gpio-pins { gpio0_pinconf { : pinctrl-namesfunction = "defaultGPIO"; pinctrl-0pins = <&typec_pins>;"GPIO0"; typec-gpios = <&pctl 98 GPIO_ACTIVE_HIGH>input-enable; input-schmitt-enable; : }; : }; |
where property pinctrl-0 sets up pins of uphy@f80bd000 device for "default" state. It is a handle (an address) to sub-node of pin-controller node.
Property typec-gpios defines one GPIO pin to GPIO98 of pin controller. Linux driver can get GPIO descriptors using the property. pctl is a handle (an address) to pin controller.
The following device-tree source of SP7350 shows definitions of sub-node pinmux_typec-pins of node pinctrl@f8800080.
Code Block | ||
---|---|---|
| ||
typec_pins: pinmux_typec-pins { gpio1_pinconf { function = "GPIO"; pins = "GPIO98"; };GPIO1"; output-enable; output-low; drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_1100_IOL_1100UA>; }; }; |
In the extra_gpio-pins node, GPIO0 is configured as an input with Schmitt trigger. Meanwhile, GPIO1 is configured as an output set to low, with a specified drive strength.
Special Function Pins
Some devices pins of SP7350 are multiplexed to specified pin-group of SP7350. This section explains how to modify device-tree source file to enable pins of those devices.
Every device should have a node in device-tree source (dts) file in Linux. Property pinctrl-0 (or pinctrl-1, pinctrl-2,… if a device has more states) is used to point at pin configuration node within pin controller (node pinctrl@f8800080 in SP7021). Pin configuration nodes (sub-nodes in node pinctrl@f8800080 ) define the actual pins assignment. For examples:
pinmux
eMMC device:
Pins of eMMC of SP7350, [D5, D3, D4, D0, D1, CLK, D2, D7, D6, CMD, DS], can be multiplexed to pin-group GPIO [20, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37].
...
Refer to "Function-group Table" in Appendix.
pinconf
One configuration Configuration to all pinsAll Pins.
Pin configuration will be applied to all pins included by property "pins" or "groups". For example:
...
"drive-strength-microamp = <SPPCTRL_DVIO_DRV_IOH_15200_IOL_18700UA>;" indicates that setting drive strength to 15.2mA on GPIO50 and GPIO51 included by group "UART0_X1".
Different configurations Configurations to different pinsDifferent Pins.
If users want to set different drive strength on GPIO50 and GPIO51 respectively,do as below:
...
Other supported pin configurations are supposed to be configurated configured in the same way.
Here lists some examples of pin configuration on sp7350-ev.dts:
...
Code Block | ||
---|---|---|
| ||
uadbg_pins: pinmux_uadbg-pins {
function = "UADBG";
groups = "UADBG";
drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_6600_IOL_6600UA>;
}; |
UART6 with typical drive source current 6.6mA (Min: 4.5mA, Max: 8.6mA) for GPIO.
Code Block | ||
---|---|---|
| ||
uart6_pins: pinmux_uart6-pins {
function = "UART6";
groups = "UART6_X1";
drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_6600_IOL_6600UA>;
}; |
...
UART6 with typical drive source current 6.6mA (Min: 4.5mA, Max: 8.6mA) for GPIO.
Code Block | ||
---|---|---|
| ||
uart7uart6_pins: pinmux_uart7uart6-pins { function = "UART7UART6"; groups = "UART7UART6_X1"; drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_6600_IOL_6600UA>; }; |
Refer to Driving-strength Table of GPIO and Driving-strength Table of DVIO in Appendix.
Appendix
List of support properties
...
Properties
...
Values
...
Descriptions
...
bias-disable
...
NA
...
Disable pull-up, pull-down and strong pull-up
...
bias-high-impedance
...
NA
...
bias-pull-up
...
NA
...
bias-pull-down
...
NA
...
drive-open-drain
...
NA
...
drive-strength-microamp
...
UART7 with typical drive source current 6.6mA (Min: 4.5mA, Max: 8.6mA) for GPIO.
Code Block | ||
---|---|---|
| ||
uart7_pins: pinmux_uart7-pins {
function = "UART7";
groups = "UART7";
drive-strength-microamp = <SPPCTRL_GPIO_DRV_IOH_6600_IOL_6600UA>;
}; |
Refer to Driving-strength Table of GPIO and Driving-strength Table of DVIO in Appendix.
...
function
...
…
...
Refer to Function-group Table
...
groups
...
…
...
Refer to Function-group Table
...
input-disable
...
NA
...
input-enable
...
NA
...
input-schmitt-disable
...
NA
...
input-schmitt-enable
...
NA
...
Appendix
List of Support Properties
GPIO #
Power domain
Pin type
Pin name
Power-supply
0 - 19
Main
1.8V GPIO
G_MX0 - G_MX19
VDDPST18_GPIO
20
1.8V/3.0V DVIO
G_MX20
VDDPST3018_DVIO_2
21 - 27
Properties | Values | Descriptions | ||||||||
bias-disable | NA | output-enable | NA | output-high | NA | output-low | NA | pins | “GPIO0” ~ “GPIO105” | sunplus,bias-strong-pull-upDisable pull-up, pull-down and strong pull-up |
bias-high-impedance | NA | |||||||||
bias-pull-up | NA | |||||||||
bias-pull-down | NA | |||||||||
drive-open-drain | NA | For GPIO only, excluding or DVIO | ||||||||
sunplus,inputdrive-invertstrength-disablemicroamp | NA | sunplus,input-invert-enable | NA | |||||||
sunplus,ms-dvio-group-0 | “1V8” or “3V0” | For G_MX21 - G_MX27 | ||||||||
sunplus,ms-dvio-group-1 | “1V8” or “3V0” | For G_MX20, G_MX28 - G_MX37 | ||||||||
sunplus,ms-dvio-ao-group-0 | “1V8” or “3V0” | For AO_MX0 - AO_MX9 | ||||||||
sunplus,ms-dvio-ao-group-1 | “1V8” or “3V0” | For AO_MX10 - AO_MX19 | ||||||||
sunplus,ms-dvio-ao-group-2 | “1V8” or “3V0” | For AO_MX20 - AO_MX29 | sunplus,output-invert-disable | NA | sunplus,output-invert-enable | NA | sunplus,slew-rate-control-disable | NA | sunplus,slew-rate-control-enable | NA |
GPIO Table
28 - 37
… | Refer to Driving-strength Table of GPIO and DVIO. | |
function | … | Refer to Function-group Table |
groups | … | Refer to Function-group Table |
input-disable | NA | For GPIO or DVIO |
input-enable | NA | For GPIO or DVIO |
input-schmitt-disable | NA | |
input-schmitt-enable | NA | |
output-disable | NA | For GPIO or DVIO |
output-enable | NA | For GPIO or DVIO |
output-high | NA | For GPIO or DVIO |
output-low | NA | For GPIO or DVIO |
pins | “GPIO0” ~ “GPIO105” | |
sunplus,bias-strong-pull-up | NA | For GPIO only, excluding DVIO |
sunplus,input-invert-disable | NA | For GPIO or DVIO |
sunplus,input-invert-enable | NA | For GPIO or DVIO |
sunplus,ms-dvio-group-0 | “1V8” or “3V0” | For G_MX21 - G_MX27 |
VDDPST3018_DVIO_1
50 - 59
CM4 (AO)
sunplus,ms-dvio-group-1 | “1V8” or “3V0” | For G_MX20, G_MX28 - G_MX37 |
VDDPST3018_DVIO_2
38 - 43
G_MX38 - G_MX43
AVDDIO_3018_SD
44 - 49
G_MX44 - G_MX49
AVDDIO_3018_SDIO
sunplus,ms-dvio-ao-group-0 | “1V8” or “3V0” | For AO_MX0 - AO_MX9 |
VDDPST3018_DVIO_AO_1
60 - 69
AO_MX10 - AO_MX19
VDDPST3018_DVIO_AO_2
70 - 79
sunplus,ms-dvio-ao-group-1 | “1V8” or “3V0” | For AO_MX10 - AO_MX19 |
sunplus,ms-dvio-ao-group-2 | “1V8” or “3V0” | For AO_MX20 - AO_MX29 |
VDDPST3018_DVIO_AO_3
80 - 98
1.8V GPIO
AO_MX30 - AO_MX48
VDDPST18_GPIO_AO
99 - 105
sunplus,output-invert-disable | NA | For GPIO or DVIO |
sunplus,output-invert-enable | NA | For GPIO or DVIO |
sunplus,slew-rate-control-disable | NA | |
sunplus,slew-rate-control-enable | NA |
Driving-strength Table of GPIO
# | Source current (mA) | Sink current (mA) | MACRO | ||||
Min. | Typ. | Max. | Min. | Typ. | Max. | ||
0 | 0.8 | 1.1 | 1.5 | 0.7 | 1.1 | 1.6 | SPPCTRL_GPIO_DRV_IOH_1100_IOL_1100UA |
1 | 1.1 | 1.6 | 2.2 | 1.1 | 1.7 | 2.3 | SPPCTRL_GPIO_DRV_IOH_1600_IOL_1700UA |
2 | 2.3 | 3.3 | 4.3 | 2.1 | 3.3 | 4.7 | SPPCTRL_GPIO_DRV_IOH_3300_IOL_3300UA |
3 | 3.4 | 4.9 | 6.5 | 3.2 | 5.0 | 7.0 | SPPCTRL_GPIO_DRV_IOH_4900_IOL_5000UA |
4 | 4.5 | 6.6 | 8.6 | 4.2 | 6.6 | 9.3 | SPPCTRL_GPIO_DRV_IOH_6600_IOL_6600UA |
5 | 5.7 | 8.2 | 10.8 | 5.3 | 8.3 | 11.7 | SPPCTRL_GPIO_DRV_IOH_8200_IOL_8300UA |
6 | 6.8 | 9.9 | 13.0 | 6.3 | 9.9 | 13.9 | SPPCTRL_GPIO_DRV_IOH_9900_IOL_9900UA |
7 | 7.9 | 11.5 | 15.1 | 7.4 | 11.6 | 16.2 | SPPCTRL_GPIO_DRV_IOH_11500_IOL_11600UA |
8 | 9.0 | 13.1 | 17.2 | 8.4 | 13.2 | 18.5 | SPPCTRL_GPIO_DRV_IOH_13100_IOL_13200UA |
9 | 10.2 | 14.8 | 19.4 | 9.4 | 14.8 | 20.8 | SPPCTRL_GPIO_DRV_IOH_14800_IOL_14800UA |
10 | 11.3 | 16.4 | 21.6 | 10.5 | 16.5 | 23.1 | SPPCTRL_GPIO_DRV_IOH_16400_IOL_16500UA |
11 | 12.4 | 18.1 | 23.7 | 11.5 | 18.1 | 25.4 | SPPCTRL_GPIO_DRV_IOH_18100_IOL_18100UA |
12 | 13.5 | 19.6 | 25.8 | 12.6 | 19.7 | 27.6 | SPPCTRL_GPIO_DRV_IOH_19600_IOL_19700UA |
13 | 14.7 | 21.3 | 28.0 | 13.6 | 21.4 | 29.9 | SPPCTRL_GPIO_DRV_IOH_21300_IOL_21400UA |
14 | 15.8 | 22.9 | 30.1 | 14.6 | 23.0 | 32.1 | SPPCTRL_GPIO_DRV_IOH_22900_IOL_23000UA |
15 | 16.9 | 24.6 | 32.3 | 15.7 | 24.6 | 34.4 | SPPCTRL_GPIO_DRV_IOH_24600_IOL_24600UA |
Driving-strength Table of DVIO
# | Source current (mA) | Sink current (mA) | MACRO | ||||
Min. | Typ. | Max. | Min. | Typ. | Max. | ||
0 | 1.9 | 5.1 | 9.9 | 4.0 | 6.2 | 8.6 | SPPCTRL_DVIO_DRV_IOH_5100_IOL_6200UA |
1 | 2.8 | 7.6 | 14.8 | 6.0 | 9.3 | 12.9 | SPPCTRL_DVIO_DRV_IOH_7600_IOL_9300UA |
2 | 3.7 | 10.1 | 19.8 | 8.1 | 12.5 | 17.1 | SPPCTRL_DVIO_DRV_IOH_10100_IOL_12500UA |
3 | 4.6 | 12.6 | 24.7 | 10.1 | 15.6 | 21.4 | SPPCTRL_DVIO_DRV_IOH_12600_IOL_15600UA |
4 | 5.6 | 15.2 | 29.7 | 12.1 | 18.7 | 25.7 | SPPCTRL_DVIO_DRV_IOH_15200_IOL_18700UA |
5 | 6.5 | 17.7 | 34.6 | 14.1 | 21.8 | 29.9 | SPPCTRL_DVIO_DRV_IOH_17700_IOL_21800UA |
6 | 7.4 | 20.2 | 39.5 | 16.1 | 24.9 | 34.2 | SPPCTRL_DVIO_DRV_IOH_20200_IOL_24900UA |
7 | 8.3 | 22.7 | 44.3 | 18.1 | 27.9 | 38.4 | SPPCTRL_DVIO_DRV_IOH_22700_IOL_27900UA |
8 | 9.3 | 25.2 | 49.3 | 20.1 | 31.0 | 42.7 | SPPCTRL_DVIO_DRV_IOH_25200_IOL_31000UA |
9 | 10.2 | 27.7 | 54.2 | 22.1 | 34.1 | 46.9 | SPPCTRL_DVIO_DRV_IOH_27700_IOL_34100UA |
10 | 11.1 | 30.3 | 59.1 | 24.1 | 37.2 | 51.1 | SPPCTRL_DVIO_DRV_IOH_30300_IOL_37200UA |
11 | 12.0 | 32.8 | 64.0 | 26.1 | 40.3 | 55.3 | SPPCTRL_DVIO_DRV_IOH_32800_IOL_40300UA |
12 | 13.0 | 35.3 | 68.9 | 28.1 | 43.4 | 59.5 | SPPCTRL_DVIO_DRV_IOH_35300_IOL_43400UA |
13 | 13.9 | 37.8 | 73.7 | 30.1 | 46.4 | 63.8 | SPPCTRL_DVIO_DRV_IOH_37800_IOL_46400UA |
14 | 14.8 | 40.3 | 78.6 | 32.1 | 49.5 | 67.9 | SPPCTRL_DVIO_DRV_IOH_40300_IOL_49500UA |
15 | 15.7 | 42.7 | 83.4 | 34.1 | 52.6 | 72.1 | SPPCTRL_DVIO_DRV_IOH_42700_IOL_52600UA |
Function-pin Table
function name
pins name
binding pins
GPIO
“GPIO0” ~ “GPIO105”
Function-group Table
function name | groups name | binding pins |
SPI_FLASH | SPI_FLASH | 21, 22, 23, 24, 25, 26 |
EMMC | EMMC | 20, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 |
SPI_NAND | SPI_NAND_X1 | 30, 31, 32, 33, 34, 35 |
SPI_NAND_X2 | 21, 22, 23, 24, 25, 26 | |
SD_CARD | SD_CARD | 38, 39, 40, 41, 42, 43 |
SDIO | SDIO | 44, 45, 46, 47, 48, 49 |
PARA_NAND | PARA_NAND | 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36 |
USB_OTG | USB_OTG | 18, 19 |
GMAC | GMAC_RGMII | 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 |
GMAC_RMII | 4, 5, 6, 7, 8, 9, 10, 11, 12 | |
PWM0 | PWM0_X1 | 78 |
PWM0_X2 | 58 | |
PWM1 | PWM1_X1 | 79 |
PWM1_X2 | 59 | |
PWM2 | PWM2_X1 | 60 |
PWM2_X2 | 92 | |
PWM3 | PWM3_X1 | 61 |
PWM3_X2 | 93 | |
UART0 | UART0_X1 | 50, 51 |
UART0_X2 | 68, 69 | |
UART1 | UART1_X1 | 52, 53 |
UART1_X2 | 64, 65 | |
UART1_FC | UART1_FC_X1 | 54, 55 |
UART1_FC_X2 | 66, 67 | |
UART2 | UART2_X1 | 56, 57 |
UART2_X2 | 76, 77 | |
UART2_FC | UART2_FC_X1 | 58, 59 |
UART2_FC_X2 | 78, 79 | |
UART3 | UART3_X1 | 62, 63 |
UART3_X2 | 7, 8 | |
UADBG | UADBG | 13, 14 |
UART6 | UART6_X1 | 80, 81 |
UART6_X2 | 48, 49 | |
UART7 | UART7 | 82, 83 |
I2C_COMBO0 | I2C_COMBO0_X1 | 68, 69 |
I2C_COMBO0_X2 | 54, 55 | |
I2C_COMBO1 | I2C_COMBO1 | 70, 71 |
I2C_COMBO2 | I2C_COMBO2_X1 | 76, 77 |
I2C_COMBO2_X2 | 56, 57 | |
I2C_COMBO3 | I2C_COMBO3 | 88, 89 |
I2C_COMBO4 | I2C_COMBO4 | 90, 91 |
I2C_COMBO5 | I2C_COMBO5 | 92, 93 |
I2C_COMBO6 | I2C_COMBO6_X1 | 84, 85 |
I2C_COMBO6_X2 | 1, 2 | |
I2C_COMBO7 | I2C_COMBO7_X1 | 86, 87 |
I2C_COMBO7_X2 | 3, 4 | |
I2C_COMBO8 | I2C_COMBO8_X1 | 95, 96 |
I2C_COMBO8_X2 | 9, 10 | |
I2C_COMBO9 | I2C_COMBO9_X1 | 97, 98 |
I2C_COMBO9_X2 | 11, 12 | |
SPI_MASTER0 | SPI_MASTER0_X1 | 64, 65, 66, 67 |
SPI_MASTER0_X2 | 9, 10, 11, 12 | |
SPI_MASTER1 | SPI_MASTER1_X1 | 80, 81, 82, 83 |
SPI_MASTER1_X2 | 14, 15, 16, 17 | |
SPI_MASTER2 | SPI_MASTER2 | 88, 89, 90, 91 |
SPI_MASTER3 | SPI_MASTER3_X1 | 44, 45, 46, 47 |
SPI_MASTER3_X2 | 52, 53, 54, 55 | |
SPI_MASTER4 | SPI_MASTER4 | 72, 73, 74, 75 |
SPI_SLAVE0 | SPI_SLAVE0_X1 | 94, 95, 96, 97 |
SPI_SLAVE0_X2 | 72, 73, 74, 75 | |
AUD_TDMTX_XCK | AUD_TDMTX_XCK | 93 |
AUD_DAC_XCK1 | AUD_DAC_XCK1 | 71 |
AUD_DAC_XCK | AUD_DAC_XCK | 83 |
AUD_AU2_DATA0 | AUD_AU2_DATA0 | 82 |
AUD_AU1_DATA0 | AUD_AU1_DATA0 | 58 |
AUD_AU2_CK | AUD_AU2_CK | 80, 81 |
AUD_AU1_CK | AUD_AU1_CK | 56, 57 |
AUD_AU_ADC_DATA0 | AUD_AU_ADC_DATA0_X1 | 94, 95, 96, 97 |
AUD_AU_ADC_DATA0_X2 | 72, 73, 74, 75 | |
AUD_ADC2_DATA0 | AUD_ADC2_DATA0 | 82 |
AUD_ADC1_DATA0 | AUD_ADC1_DATA0 | 58 |
AUD_TDM | AUD_TDM | 94, 95, 96, 97 |
SPDIF_IN | SPDIF_IN_X1 | 91 |
SPDIF_IN_X2 | 53 | |
SPDIF_IN_X3 | 54 | |
SPDIF_IN_X4 | 55 | |
SPDIF_IN_X5 | 62 | |
SPDIF_IN_X6 | 52 | |
SPDIF_OUT | SPDIF_OUT_X1 | 91 |
SPDIF_OUT_X2 | 53 | |
SPDIF_OUT_X3 | 54 | |
SPDIF_OUT_X4 | 55 | |
SPDIF_OUT_X5 | 62 | |
SPDIF_OUT_X6 | 52 | |
INT0 | INT0_X1 | 1 |
INT0_X2 | 2 | |
INT0_X3 | 3 | |
INT0_X4 | 4 | |
INT0_X5 | 5 | |
INT0_X6 | 6 | |
INT0_X7 | 13 | |
INT0_X8 | 14 | |
INT0_X9 | 15 | |
INT1 | INT1_X1 | 1 |
INT1_X2 | 2 | |
INT1_X3 | 3 | |
INT1_X4 | 4 | |
INT1_X5 | 5 | |
INT1_X6 | 6 | |
INT1_X7 | 13 | |
INT1_X8 | 14 | |
INT1_X9 | 15 | |
INT2 | INT2_X1 | 5 |
INT2_X2 | 6 | |
INT2_X3 | 7 | |
INT2_X4 | 8 | |
INT2_X5 | 9 | |
INT2_X6 | 10 | |
INT2_X7 | 11 | |
INT2_X8 | 16 | |
INT2_X9 | 17 | |
INT3 | INT3_X1 | 5 |
INT3_X2 | 6 | |
INT3_X3 | 7 | |
INT3_X4 | 8 | |
INT3_X5 | 9 | |
INT3_X6 | 10 | |
INT3_X7 | 11 | |
INT3_X8 | 16 | |
INT3_X9 | 17 | |
INT4 | INT4_X1 | 7 |
INT4_X2 | 8 | |
INT4_X3 | 9 | |
INT4_X4 | 10 | |
INT4_X5 | 11 | |
INT4_X6 | 12 | |
INT4_X7 | 13 | |
INT4_X8 | 18 | |
INT4_X9 | 19 | |
INT5 | INT5_X1 | 7 |
INT5_X2 | 8 | |
INT5_X3 | 9 | |
INT5_X4 | 10 | |
INT5_X5 | 11 | |
INT5_X6 | 12 | |
INT5_X7 | 13 | |
INT5_X8 | 18 | |
INT5_X9 | 19 | |
INT6 | INT6_X1 | 9 |
INT6_X2 | 10 | |
INT6_X3 | 11 | |
INT6_X4 | 12 | |
INT6_X5 | 13 | |
INT6_X6 | 14 | |
INT6_X7 | 15 | |
INT6_X8 | 16 | |
INT6_X9 | 17 | |
INT6_X10 | 18 | |
INT6_X11 | 19 | |
INT7 | INT7_X1 | 9 |
INT7_X2 | 10 | |
INT7_X3 | 11 | |
INT7_X4 | 12 | |
INT7_X5 | 13 | |
INT7_X6 | 14 | |
INT7_X7 | 15 | |
INT7_X8 | 16 | |
INT7_X9 | 17 | |
INT7_X10 | 18 | |
INT7_X11 | 19 | |
GPIO_AO_INT0 | GPIO_AO_INT0_X1 | 52, 53, 54, 55, 56, 57, 58, 59 |
GPIO_AO_INT0_X2 | 68, 69, 70, 71, 72, 73, 74, 75 | |
GPIO_AO_INT1 | GPIO_AO_INT1_X1 | 60, 61, 62, 63, 64, 65, 66, 67 |
GPIO_AO_INT1_X2 | 76, 77, 78, 79, 80, 81, 82, 83 | |
GPIO_AO_INT2 | GPIO_AO_INT2_X1 | 68, 69, 70, 71, 72, 73, 74, 75 |
GPIO_AO_INT2_X2 | 84, 85, 86, 87, 88, 89, 90, 91 | |
GPIO_AO_INT3 | GPIO_AO_INT3_X1 | 76, 77, 78, 79, 80, 81, 82, 83 |
GPIO_AO_INT3_X2 | 91, 92, 93, 94, 95, 96, 97, 98 |