Page Comparison

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Subsequently, x-boot loads the images of TF-A (BL31), OP-TEE (BL32), and U-Boot (BL33) from a storage device into DRAM. The CPU (core 0) then switches itself from 32-bit mode to 64-bit by triggering a software reset. It proceeds to awaken other cores (core 1, 2, 3) and transitions them to 64-bit mode. Finally, all cores execute TF-A.

Table of Contents

Features

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The flow chart below illustrates the process from i-boot's reset vector to the jump to TF-A for all cores

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Source

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Files

The source files for x-boot are located in the "boot/xobot/" directory under the project's top folder. The entry point for x-boot is the label "_start" in the assembly file "arch/arm/sp7350/start.S". Notably, "_start" is situated at an offset of 32 bytes within the x-boot module, with the initial 32-byte space reserved for a header. The "_start" subroutine initializes the C execution environment and subsequently jumps to the C main function, the "xboot_main()" subroutine in the "xboot.c" file. The "xboot.c" file serves as the top-level control file for x-boot, governing the entire flow of operations.

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Driver

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Specifications and

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Features

x-boot incorporates a range of device drivers, each offering specific features to facilitate various operations. The following table outlines the detailed specifications and features of these drivers.

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During system boot, i-boot reads boot-related information from the boot switch and the OTP (One-Time Programmable) memory within the chip. This information is then stored in the C structure g_bootinfo. x-boot directly utilizes the data in the g_bootinfo structure to determine the boot mode and process.

x-boot Log and Explanation

Line 1: Banner (version) of x-boot

Line 5: PLLC (CPU frequency) is set to 1.5GHz.

Line 6: PLLL3 (L3 cache frequency) is configured to 1.2GHz.

Line 7: PLLD (DRAM clock) is set to 800MHz, with a data-rate of DDR SDRAM is 3200 Mbps.

Line 14: “{{emmc_boot}}” indicates that x-boot is executing the 'emmc boot' flow.

Line 19: Boot-device is 0x1F (MX[6..2]), indicating eMMC boot.

Line 20: Banner (version) of DDR training firmware

Line 23: DDR SDRAM part number is MT53E1G32D2 version B, with FBGA code ‘D8CJG’.

LIne 24: DDR SDRAM clock is at 1600MHz.

Line 28: The length of the x-boot image is 0xAEA0 (44,704 bytes), excluding DDR training firmware.

Line 29-30: 1D training firmware has benn successfully loaded, with the checksum verified.

Line 42: 1D training has successfully completed.

Line 44-45: 2D training firmware has been successfully loaded, with the checksum verified.

Line 52: 2D training has successfully completed.

LIne 57: Testing DRAM (only 1kB range)

Line 61: The bus clock of eMMC is configured to 200kHz (divisor = 1789) for the IdentifyStorage command.

Line 69: The bus clock of eMMC is adjusted to 25MHz (divisor = 14) for subsequent Read and other commands.

Line 70: Read GPT of eMMC.

LIne 71-73: Loading header of uboot1 image (factory default)

Line 74-78: Loading uboot2 image (the latest update). Size of uboot2 image is 858,952 bytes. The checksum of uboot2 image is successfully verified.

Line 79-81: Loading fip image (including TF-A and OP-TEE images). Size of fip image is 408,462 bytes. The checksum of fip image is successfully verified.

Line 82: uboot image is loaded at 0x00500040.

Line 83: fip image is loaded at 0x01000000.

Line 84: Initializing Cortex M4 hardware. Reset of CM4 is asserted here.

Line 85-86: CPU core is preparing to switch to 64-bit mode, and a64up module is located at 0xFA218400.

Line 87: CPU core 0 is at secure EL3 mode and proceeds to execute TF-A (BL31), which is located at 0x00200000.

+++xBoot Feb 14 2024 18:41:41
Remap DRAM for 4GB
ID1 of STI8070X = 0x88
ID2 of STI8070X = 0x01
Set PLLC to 1.5GHz
Set PLLL3 to 1.2GHz
PLLD: 800MHz, DATARATE:3200
0x00001008
0x0000C0BE
0x00000107
[d] xboot.c :397
..mode=0x0000001F

{{emmc_boot}}
[d] common/bootmain.c :76
dev=2
pin=1
.Run draiminit@0xFA208351
bootdevice=0x0000001F
Built at Feb 14 2024 18:41:37
dram_init
dwc_umctl2_lpddr4_1600_SP7350_for_realchip
MT53E1G32D2_B, 2rank, FBGA=D8CJG
SDRAM_SPEED_1600
dwc_ddrphy_phyinit_main 20231212
dwc_ddrphy_phyinit_out_lpddr4_train1d2d_3200_SP7350
bootdevice:0x0000001F
XBOOT_len=0x0000AEA0
1D IMEM checksum ok
1D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of CA training.
End of initialization.
End of read enable training.
End of fine write leveling.
End of read dq deskew training.
End of MPR read delay center optimization.
End of Wrtie leveling coarse delay.
End of write delay center optimization.
End of read delay center optimization.
End of max read latency training.
Training has run successfully.(firmware complete)
bootdevice:0x0000001F
2D IMEM checksum ok
2D DMEM checksum ok
Start to wait for the training firmware to complete v.00 !!!
End of initialization.
End of 2D write delay/voltage center optimization.
End of 2D write delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
End of 2D read delay/voltage center optimization.
Training has run successfully.(firmware complete)
Register programming done!!!
Register programming done!!!
dram_init_end
Done draiminit
dram test 0x00800000 - 0x00800400
Set WL_REG_ON (GPIO56) to HI.
[d] sdmmc/drv_sd_mmc.c :21
InitChipCtrl
busclk=200000
div=1789
[d] sdmmc/drv_sd_mmc.c :23
IdentifyStorage
[d] sdmmc/hal_sd_mmc.c :507
busclk=25000000
div=14
[d] sdmmc/hal_sd_mmc.c :1729
[d] sdmmc/drv_sd_mmc.c :33
Read GPT
part1 LBA=0x00000022
emmc load uboot@blk=0x00000022
uboot1 hdr good
part2 LBA=0x00000822
emmc load uboot@blk=0x00000822
data size=858952
verify img...
uboot2 good
emmc load fip@blk=0x00001022
data size=408462
verify img...
uboot @0x00500040
fip @0x01000000
M4 init
32->64
a64up@0xFA218400
core0 S-EL3 @0x00200000